SM59A16U1
8-Bit Micro-controller
64KB with ISP Flash
& 6K+256B RAM embedded
10.1
Watchdog Timer Control Register( WDTC )
Mnemonic: WDTC
Address: B6h
7
-
6
5
4
-
3
2
1
0
Reset
04H
CWDTR
WDTE
WDTM [3:0]
CWDTR: Watch dog states select bit(Support stop mode wakeup)
CWDTR = 0 - Enable watch dog reset.
CWDTR = 1 - Enable watch dog interrupt.
WDTE: Control bit used to enable Watchdog timer.
The WDTE bit can be used only if WDTEN is "0". If the WDTEN bit is "0", then WDT
can be disabled / enabled by the WDTE bit.
WDTE = 0 - Disable WDT.
WDTE = 1 - Enable WDT.
The WDTE bit is not used if WDTEN is "1". That is, if the WDTEN bit is "1", WDT is
always disabled no matter what the WDTE bit status is. The WDTE bit can be read
and written.
WDTM [3:0]: WDT clock source divider bit. Please see Table 10-1 to reference the WDT time-out
period.
10.2
Watchdog Timer Refresh Register( WDTK )
Mnemonic: WDTK
Address: B7h
7
6
5
4
3
2
1
0
Reset
00H
WDTK[7:0]
WDTK[7:0] : Watchdog timer refresh key.
A programmer must to write 0x55 into WDTK register, the watchdog timer will be clear to zero.
For example, if enable WDT and select time-out reset period is 2.8493s.
First, programming the information block OP3 bit7 WDTEN to “0”.
Secondly,
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah ; enable WDTC write attribute.
MOV WDTC, #28h
; Set WDTM [3:0] = 1000b. Set WDTE =1 to enable WDT function.
.
.
.
MOV WDTK, #55h
; Clear WDT timer to 0.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M071 Ver A SM59A16U1 04/12/2013
- 73 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
