SM59A16U1
8-Bit Micro-controller
64KB with ISP Flash
& 6K+256B RAM embedded
10. Watchdog timer
The Watch Dog Timer (WDT) is an 8-bit free-running counter that generate reset signal if the counter overflows. The
WDT is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing
software dead loop or runaway. The WDT function can help user software recover from abnormal software condition.
The WDT is different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by
software periodically clearing the WDT counter. User should check WDTF bit of WDTC register whenever un-predicted
reset happened. After an external reset the watchdog timer is disabled and all registers are set to zeros.
The watchdog timer has a free running on-chip RC oscillator (23 KHz). The WDT will keep on running even after the
system clock has been turned off (for example, in sleep mode). During normal operation or sleep mode, a WDT time-
out (if enabled) will cause the MCU to reset. The WDT can be enabled or disabled any time during the normal mode.
Please refer the WDTE bit of WDTC register. The default WDT time-out period is approximately 178.0ms (WDTM [3:0]
= 0100b).
The WDT has selectable divider input for the time base source clock. To select the divider input, the setting of bit3 ~
bit0 (WDTM [3:0]) of Watch Dog Timer Control Register (WDTC) should be set accordingly. As shown in Table 10-1.
23KHz
WDTCLK
2WDTM
256
Watchdog reset time =
WDTCLK
Table 10-1: WDT time-out period
Divider
(23 KHz RC oscillator in)
WDTM [3:0]
Time period @ 23KHz
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
2
4
8
16
11.1ms
22.2ms
44.5ms
89.0ms
178.0ms (default)
356.1ms
712.3ms
1.4246s
32
64
128
256
512
1024
2048
4096
8192
16384
32768
2.8493s
5.6987s
11.397s
22.795s
45.590s
91.180s
182.36s
364.72s
Note: RC oscillator (23 KHz), about ± 20% of variation.
When MCU is reset, the MCU will be read WDTEN control bit status. When WDTEN bit is set to 1, the watchdog
function will be disabled no matter what the WDTE bit status is. When WDTEN bit is clear to 0, the watchdog function
will be enabled if WDTE bit is set to 1 by program. User can to set WDTEN on the writer or ISP.
The program can enable the WDT function by programming 1 to the WDTE bit premise that WDTEN control bit is clear
to 0. After WDTE set to 1, the 8 bit-counter starts to count with the selected time base source clock which set by
WDTM [3:0]. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when MCU
been reset, either hardware reset or WDT reset. As shown in Fig. 10-1.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M071
Ver A SM59A16U1 04/12/2013
- 71 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
