SMM151/152
I
2
C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS – 100kHz
T
A
= 0°C to +70°C, VDD = 2.7V to 5.5V unless otherwise noted. All voltages are relative to GND. See Figure 3 Timing
Diagram. Note 6.
Symbol
f
SCL
t
LOW
t
HIGH
t
BUF
t
SU:STA
t
HD:STA
t
SU:STO
t
AA
t
DH
t
R
t
F
t
SU:DAT
t
HD:DAT
TI
t
WR
Description
SCL Clock Frequency
Clock Low Period
Clock High Period
Bus Free Time
Start Condition Setup Time
Start Condition Hold Time
Stop Condition Setup Time
Clock Edge to Data Valid
Data Output Hold Time
SCL and SDA Rise Time
SCL and SDA Fall Time
Data In Setup Time
Data In Hold Time
Noise Filter SCL and SDA
Write Cycle Time
Conditions
Min
0
4.7
4.0
Typ
Max
100
Units
KHz
μs
μs
μs
μs
μs
μs
Before New Transmission, Note 5
4.7
4.7
4.0
4.7
SCL low to valid SDA (cycle n)
SCL low (cycle n+1) to SDA
change
Note 5
Note 5
0.2
0.2
3.5
μs
μs
1000
300
250
0
ns
ns
ns
ns
Noise suppression
100
5
ns
ms
Note 5: Not 100% Production tested. Guaranteed by Design and/or Characterization.
Note 6: All electrical parameters are guaranteed to function over the stated VDD, VCS and temperature range. Electrical parameters not specified as
"guaranteed by design" are tested with a VDD voltage required of the specific application. For example, if the device is to be operated at 3.3V and VCS
supply of 12V, it is tested with a VDD supply of 3.3V, +-10% and a VCS supply of 12V, +-10%.
TIMING DIAGRAMS
t
R
SCL
t
SU:STA
SDA
(IN)
t
AA
SDA
(OUT)
t
F
t
HD:STA
t
HIGH
t
WR (For Write Operation Only)
t
LOW
t
SU:DAT
t
SU:STO
t
BUF
t
HD:DAT
t
DH
Figure 3. Basic I
2
C Serial Interface Timing
Summit Microelectronics, Inc
2131 3.0 1/20/2010
9
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
