VND5012AK-E
Figure 2. Block Diagram
V
CC
UNDERVOLTAGE
V
CC
CLAMP
OUTPUT1
PwCLAMP 1
CURRENT
SENSE1
GND
DRIVER 1
I
1
LIM
PwCLAMP 2
INPUT1
DRIVER 2
V
1
LOGIC
DSLIM
OUTPUT2
Pwr
1
LIM
I
2
LIM
CURRENT
SENSE2
OVERTEMP. 1
K 1
V
2
DSLIM
INPUT2
CS_DIS
I
OUT1
OVERTEMP. 2
K 2
I
OUT2
Pwr
2
LIM
Table 3. Pin Function
Name
Function
V
Battery connection
Power output
CC
OUTPUT
GND
1,2
Ground connection. Must be reverse battery protected by an external diode/resistor network
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state
Analog current sense pin, delivers a current proportional to the load current
Active high CMOS compatible pin, to disable the current sense pin
INPUT
1,2
CURRENT SENSE
CS_DIS
1,2
Figure 3. Current and Voltage Conventions
I
S
V
CC
V
CC
V
F (*)
I
OUT1
I
CSD
OUTPUT1
CS_DIS
INPUT1
INPUT2
V
OUT1
V
CSD
I
SENSE1
CURRENT
SENSE1
I
I
IN1
IN2
V
SENSE1
V
IN1
I
OUT2
OUTPUT2
V
OUT2
V
IN2
I
SENSE2
CURRENT
SENSE2
GND
V
SENSE2
I
GND
(*) V = V - V during reverse battery condition
OUTn
Fn
CC
2/13
STMICROELECTRONICS [ ST ]
