VND5012AK-E
Figure 5.
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
t
t
DSENSE1L
t
DSENSE2H
t
DSENSE1H
DSENSE2L
Figure 6.
V
OUT
90%
80%
dV /dt
OUT (off)
dV /dt
OUT (on)
10%
t
f
t
r
t
INPUT
t
d(on)
t
d(off)
t
Table 12. Electrical Transient Requirements
ISO T/R 7637/1
TEST LEVELS
III
I
II
IV
Delays and
Impedance
Test Pulse
1
2
-25 V
+25 V
-25 V
-50 V
+50 V
-50 V
-75 V
+75 V
-100 V
+75 V
-6 V
-100 V
+100 V
-150 V
+100 V
-7 V
2 ms 10 Ω
0.2 ms 10 Ω
0.1 µs 50 Ω
0.1 µs 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
3a
3b
4
+25 V
-4 V
+50 V
-5 V
5
+26.5 V
+46.5 V
+66.5 V
+86.5 V
ISO T/R 7637/1
Test Pulse
TEST LEVELS RESULTS
I
II
C
C
C
C
C
E
III
C
C
C
C
C
E
IV
C
C
C
C
C
E
1
2
C
C
C
C
C
C
3a
3b
4
5
CLASS
CONTENTS
C
E
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to disturbance
and cannot be returned to proper operation without replacing the device.
7/13
STMICROELECTRONICS [ ST ]
