UPSD3212C, UPSD3212CV
Figure 14. State Sequence in uPSD321X Devices
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
Osc.
(XTAL2)
p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2
Read next
opcode and
discard
Read next
opcode
Read opcode
S1
S2
S3
S4
S5
S6
S6
S6
S6
a. 1-Byte, 1-Cycle Instruction, e.g. INC A
Read next
opcode
Read 2nd
Byte
Read opcode
S1
S2
S3
S4
S5
b. 2-Byte, 1-Cycle Instruction, e.g. ADD A, adrs
Read next
opcode and
discard
Read next
opcode and
discard
Read next
opcode and
discard
Read next
opcode
Read opcode
S1
S2
S3
S4
S5
S1
S2
S3
S4
S5
S6
c. 1-Byte, 2-Cycle Instruction, e.g. INC DPTR
No Fetch
No ALE
No Fetch
Read next
opcode and
discard
Read next
opcode
Read opcode
(MOVX)
S1
S2
S3
S4
S5
Addr
S1
S2
S3
S4
S5
S6
Data
d. 1-Byte, 2-Cycle MOVX Instruction
Access External Memory
AI06822
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