UPSD3212C, UPSD3212CV
Figure 76. ISC Timing
tISCCH
TCK
tISCCL
tISCPSU
tISCPH
TDI/TMS
t ISCPZV
tISCPCO
ISC OUTPUTS/TDO
tISCPVZ
ISC OUTPUTS/TDO
AI02865
Table 116. ISC Timing (5V Devices)
Symbol
Parameter
Conditions
Min
Max
Unit
MHz
ns
t
Clock (TCK, PC1) Frequency (except for PLD)
Clock (TCK, PC1) High Time (except for PLD)
Clock (TCK, PC1) Low Time (except for PLD)
Clock (TCK, PC1) Frequency (PLD only)
Clock (TCK, PC1) High Time (PLD only)
20
ISCCF
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 2)
(Note 2)
t
t
t
t
23
23
ISCCH
ISCCL
ns
2
MHz
ns
ISCCFP
ISCCHP
240
t
t
t
t
t
t
Clock (TCK, PC1) Low Time (PLD only)
ISC Port Set Up Time
240
7
ns
ns
ns
ns
ns
ns
ISCCLP
ISCPSU
ISCPH
ISC Port Hold Up Time
5
ISC Port Clock to Output
21
21
21
ISCPCO
ISCPZV
ISCPVZ
ISC Port High-Impedance to Valid Output
ISC Port Valid Output to High-Impedance
Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode.
2. For Program or Erase PLD only.
143/152
STMICROELECTRONICS [ ST ]
