STM8S207xx, STM8S208xx
Table 9. General hardware register map (continued)
Address
Memory and register map
Reset
Block
Register label
Register name
status
0x00 5230
0x00 5231
0x00 5232
0x00 5233
0x00 5234
0x00 5235
0x00 5236
0x00 5237
0x00 5238
0x00 5239
0x00 523A
UART1_SR
UART1_DR
UART1 status register
UART1 data register
0xC0
xx
UART1_BRR1
UART1_BRR2
UART1_CR1
UART1_CR2
UART1_CR3
UART1_CR4
UART1_CR5
UART1_GTR
UART1_PSCR
UART1 baud rate register 1
UART1 baud rate register 2
UART1 control register 1
UART1 control register 2
UART1 control register 3
UART1 control register 4
UART1 control register 5
UART1 guard time register
UART1 prescaler register
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
UART1
0x00 523B to
0x00 523F
Reserved area (5 bytes)
0x00 5240
0x00 5241
0x00 5242
0x00 5243
0x00 5244
0x00 5245
0x00 5246
005247
UART3_SR
UART3_DR
UART3 status register
UART3 data register
C0h
xx
UART3_BRR1
UART3_BRR2
UART3_CR1
UART3_CR2
UART3_CR3
UART3_CR4
UART3 baud rate register 1
UART3 baud rate register 2
UART3 control register 1
UART3 control register 2
UART3 control register 3
UART3 control register 4
Reserved
0x00
0x00
0x00
0x00
0x00
0x00
UART3
0x00 5248
0x00 5249
UART3_CR6
UART3 control register 6
0x00
0x00 524A to
0x00 524F
Reserved area (6 bytes)
Doc ID 14733 Rev 9
39/103
STMICROELECTRONICS [ ST ]
