STM8S207xx, STM8S208xx
Table 9. General hardware register map (continued)
Address
Memory and register map
Reset
Block
Register label
Register name
status
0x00 50C3
0x00 50C4
CLK_CMSR
CLK_SWR
Clock master status register
Clock master switch register
0xE1
0xE1
0bxxxx
0000
0x00 50C5
CLK_SWCR
Clock switch control register
0x00 50C6
0x00 50C7
0x00 50C8
0x00 50C9
0x00 50CA
0x00 50CB
0x00 50CC
0x00 50CD
CLK_CKDIVR
CLK_PCKENR1
CLK_CSSR
Clock divider register
Peripheral clock gating register 1
Clock security system register
Configurable clock control register
Peripheral clock gating register 2
CAN clock control register
0x18
0xFF
0x00
0x00
0xFF
0x00
xx
CLK
CLK_CCOR
CLK_PCKENR2
CLK_CANCCR
CLK_HSITRIMR
CLK_SWIMCCR
HSI clock calibration trimming register
SWIM clock control register
x0
0x00 50CE to
0x00 50D0
Reserved area (3 bytes)
0x00 50D1
0x00 50D2
WWDG_CR
WWDG_WR
WWDG control register
WWDR window register
0x7F
0x7F
WWDG
IWDG
0x00 50D3 to
0x00 50DF
Reserved area (13 bytes)
0x00 50E0
0x00 50E1
0x00 50E2
IWDG_KR
IWDG_PR
IWDG_RLR
IWDG key register
IWDG prescaler register
IWDG reload register
-
0x00
0xFF
0x00 50E3 to
0x00 50EF
Reserved area (13 bytes)
0x00 50F0
0x00 50F1
0x00 50F2
0x00 50F3
AWU_CSR1
AWU_APR
AWU_TBR
BEEP_CSR
AWU control/status register 1
AWU asynchronous prescaler buffer register
AWU timebase selection register
BEEP control/status register
0x00
0x3F
0x00
0x1F
AWU
BEEP
0x00 50F4 to
0x00 50FF
Reserved area (12 bytes)
Doc ID 14733 Rev 9
37/103
STMICROELECTRONICS [ ST ]
