Memory and register map
Table 9. General hardware register map (continued)
Address
STM8S207xx, STM8S208xx
Reset
Block
Register label
Register name
status
0x00 5320
0x00 5321
0x00 5322
0x00 5323
0x00 5324
0x00 5325
0x00 5326
0x00 5327
0x00 5328
0x00 5329
0x00 532A
0x00 532B
0x00 532C
0x00 532D
0x00 532E
0x00 532F
0x00 5330
TIM3_CR1
TIM3_IER
TIM3 control register 1
TIM3 interrupt enable register
TIM3 status register 1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
TIM3_SR1
TIM3_SR2
TIM3 status register 2
TIM3_EGR
TIM3 event generation register
TIM3 capture/compare mode register 1
TIM3 capture/compare mode register 2
TIM3 capture/compare enable register 1
TIM3 counter high
TIM3_CCMR1
TIM3_CCMR2
TIM3_CCER1
TIM3_CNTRH
TIM3_CNTRL
TIM3_PSCR
TIM3_ARRH
TIM3_ARRL
TIM3_CCR1H
TIM3_CCR1L
TIM3_CCR2H
TIM3_CCR2L
TIM3
TIM3 counter low
TIM3 prescaler register
TIM3 auto-reload register high
TIM3 auto-reload register low
TIM3 capture/compare register 1 high
TIM3 capture/compare register 1 low
TIM3 capture/compare register 2 high
TIM3 capture/compare register 2 low
0x00 5331 to
0x00 533F
Reserved area (15 bytes)
0x00 5340
0x00 5341
0x00 5342
0x00 5343
0x00 5344
0x00 5345
0x00 5346
TIM4_CR1
TIM4_IER
TIM4 control register 1
TIM4 interrupt enable register
TIM4 status register
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
TIM4_SR
TIM4
TIM4_EGR
TIM4_CNTR
TIM4_PSCR
TIM4_ARR
TIM4 event generation register
TIM4 counter
TIM4 prescaler register
TIM4 auto-reload register
0x00 5347 to
0x00 53FF
Reserved area (185 bytes)
42/103
Doc ID 14733 Rev 9
STMICROELECTRONICS [ ST ]
