STM8S903K3 STM8S903F3
Memory and register map
Address
Block
Register label
TIM1_CCR1L
TIM1_CCR2H
TIM1_CCR2L
TIM1_CCR3H
TIM1_CCR3L
TIM1_CCR4H
TIM1_CCR4L
TIM1_BKR
Register name
Reset
status
TIM1 capture/compare register 1 low
TIM1 capture/compare register 2 high
TIM1 capture/compare register 2 low
TIM1 capture/compare register 3 high
TIM1 capture/compare register 3 low
TIM1 capture/compare register 4 high
TIM1 capture/compare register 4 low
TIM1 break register
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00 5266
0x00 5267
0x00 5268
0x00 5269
0x00 526A
0x00 526B
0x00 526C
0x00 526D
0x00 526E
0x00 526F
TIM1_DTR
TIM1 dead-time register
TIM1_OISR
TIM1 output idle state register
Reserved area (147 bytes)
0x00 5270 to
0x00 52FF
TIM5
TIM5_CR1
TIM5_CR2
TIM5_SMCR
TIM5_IER
TIM5 control register 1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00 5300
0x00 5301
0x00 5302
0x00 5303
0x00 5304
0x00 5305
0x00 5306
0x00 5307
TIM5 control register 2
TIM5 slave mode control register
TIM5 interrupt enable register
TIM5 status register 1
TIM5_SR1
TIM5_SR2
TIM5_EGR
TIM5_CCMR1
TIM5 status register 2
TIM5 event generation register
TIM5 capture/compare mode register 1
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