STM8S903K3 STM8S903F3
Memory and register map
Address
Block
Register label
Register name
Reset
status
CLK_HSITRIMR HSI clock calibration trimming register
CLK_SWIMCCR SWIM clock control register
0x00
0x00 50CC
0x00 50CD
0bXXXX
XXX0
Reserved area (3 bytes)
0x00 50CE to
0x00 50D0
WWDG WWDG_CR
WWDG_WR
WWDG control register
WWDR window register
0x7F
0x7F
0x00 50D1
0x00 50D2
Reserved area (13 bytes)
0x00 50D3 to
00 50DF
IWDG
IWDG_KR
IWDG_PR
IWDG_RLR
IWDG key register
0x00 50E0
0x00 50E1
0x00 50E2
0xXX (2)
0x00
IWDG prescaler register
IWDG reload register
0xFF
Reserved area (13 bytes)
0x00 50E3 to
0x00 50EF
AWU
AWU_CSR1
AWU_APR
AWU control/status register 1
0x00
0x3F
0x00 50F0
0x00 50F1
AWU asynchronous prescaler buffer
register
AWU_TBR
BEEP_CSR
AWU timebase selection register
BEEP control/status register
0x00
0x1F
0x00 50F2
0x00 50F3
BEEP
Reserved area (12 bytes)
0x00 50F4 to
0x00 50FF
SPI
SPI_CR1
SPI_CR2
SPI control register 1
SPI control register 2
0x00
0x00
0x00 5200
0x00 5201
DocID15590 Rev 8
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STMICROELECTRONICS [ ST ]
