Pinout and pin description
STM8S903K3 STM8S903F3
5.3
Pin description TSSOP20_SO20_UFQFPN20
Table 5: TSSOP20/SO20/UFQFPN20 pin description
Input
Output
Main
Default alternate function Alternate function after remap
[option bit]
TSSOP UFQFPN Pin name
Type
function
(after
reset)
floating
wpu Ext.
interrupt
High
Speed
OD
PP
SO20
20
(1)
sink
4
5
1
2
NRST
I/O
I/O
X
Reset
(2)
PA1/ OSCIN
X
X
X
X
X
O1
O1
X
X
X
X
Port
A1
Resonator/ crystal in
Resonator/ crystal out
6
3
PA2/ OSCOUT
I/O
X
Port
A2
7
4
5
6
7
V
S
Digital ground
SS
8
VCAP
S
1.8 V regulator capacitor
Digital power supply
9
V
S
DD
10
PA3/ TIM5_CH3 [SPI_NSS]
[UART1_TX]
I/O
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HS
O3
O1
O1
O3
O3
O3
O3
O3
O4
O3
O3
X
X
Port
A3
Timer 52 channel 3
SPI master/ slave select [AFR1]/
UART1 data transmit [AFR1:0]
(3)
2
11
12
13
14
15
16
17
18
19
20
8
9
PB5/ I2C_SDA [TIM1_BKIN]
PB4/ I2C_SCL [ADC_ETR]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
T
Port
B5
I
I
C data
Timer 1 - break input [AFR4]
ADC external trigger [AFR4]
(3)
2
C clock
T
X
X
X
X
X
X
X
X
Port
B4
10
PC3/
X
X
X
X
X
X
X
X
HS
HS
HS
HS
HS
HS
HS
HS
X
X
X
X
X
X
X
X
Port
C3
Timer 1 - channel 3
Top level interrupt [AFR3] Timer
1 inverted channel 1 [AFR7]
TIM1_CH3/TLI/[TIM1_CH1N ]
11
12
13
14
15
16
17
PC4/ TIM1_CH4/
CLK_CCO/AIN2/[TIM1_CH2N]
Port
C4
Timer 1 - channel 4
/configurable clock output
Analog input 2 [AFR2]Timer 1
inverted channel 2 [AFR7]
PC5/SPI_SCK [TIM5_CH1]
PC6/ SPI_MOSI [TIM1_CH1]
PC7/ SPI_MISO [TIM1_CH2]
Port
C5
SPI clock
Timer 5 channel 1 [AFR0]
Timer 1 channel 1 [AFR0]
Timer 1 channel 2[AFR0]
Port
C6
PI master out/slave in
SPI master in/ slave out
SWIM data interface
Port
C7
(4)
PD1/ SWIM
Port
D1
PD2/AIN3/ [TIM5_CH3]
Port
D2
Analog input 3 [AFR2] Timer 52
- channel 3 [AFR1]
PD3/ AIN4/ TIM5_CH2/
ADC_ETR
Port
D3
Analog input 4 Timer 52 -
channel 2/ADC external
trigger
1
2
3
18
19
20
PD4/ TIM5_CH1/ BEEP
[UART1_CK]
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
HS
HS
HS
O3
O3
O3
X
X
X
X
X
X
Port
D4
Timer 5 - channel 1/BEEP
output
UART clock [AFR2]
PD5/ AIN5/ UART1_TX
PD6/ AIN6/ UART1_RX
Port
D5
Analog input 5/ UART1
data transmit
Port
D6
Analog input 6/ UART1
data receive
(1)
I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings ( see section
"Absolute maximum ratings").
(2)
When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is
recommended to use PA1 only in input mode if Halt/Active-halt is used in the application.
(3)
In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to V
are not implemented)
DD
(4)
The PD1 pin is in input pull-up during the reset phase and after internal reset release.
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DocID15590 Rev 8
STMICROELECTRONICS [ ST ]
