STM32F103xC, STM32F103xD, STM32F103xE
Table 35.
Symbol
t
w(CLK)
t
d(CLKL-NExL)
t
d(CLKH-NExH)
t
d(CLKL-NADVL)
t
d(CLKL-NADVH)
t
d(CLKL-AV)
t
d(CLKH-AIV)
t
d(CLKL-NOEL)
t
d(CLKH-NOEH)
t
d(CLKL-ADV)
t
d(CLKL-ADIV)
t
su(ADV-CLKH)
t
h(CLKH-ADV)
FSMC_CLK period
FSMC_CLK low to FSMC_NEx low (x = 0...2)
FSMC_CLK high to FSMC_NEx high (x = 0...2)
FSMC_CLK low to FSMC_NADV low
FSMC_CLK low to FSMC_NADV high
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
5
Electrical characteristics
Synchronous multiplexed NOR/PSRAM read timings
(1)(2)
Parameter
Min
27.7
1.5
T
HCLK
+ 2
4
Max
Unit
ns
ns
ns
ns
ns
0
ns
ns
T
HCLK
+1
T
HCLK
+ 0.5
12
0
6
ns
ns
ns
ns
ns
ns
ns
ns
FSMC_CLK high to FSMC_Ax invalid (x = 16...25) T
HCLK
+ 2
FSMC_CLK low to FSMC_NOE low
FSMC_CLK high to FSMC_NOE high
FSMC_CLK low to FSMC_AD[15:0] valid
FSMC_CLK low to FSMC_AD[15:0] invalid
FSMC_A/D[15:0] valid data before FSMC_CLK
high
FSMC_A/D[15:0] valid data after FSMC_CLK high T
HCLK
– 10
8
2
t
su(NWAITV-CLKH)
FSMC_NWAIT valid before FSMC_CLK high
t
h(CLKH-NWAITV)
1. C
L
= 15 pF.
2. Based on characterization, not tested in production.
FSMC_NWAIT valid after FSMC_CLK high
Doc ID 14611 Rev 7
67/123
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