Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings
tw(CLK)
FSMC_CLK
td(CLKL-NExL)
FSMC_NEx
td(CLKL-NADVL)
FSMC_NADV
td(CLKL-AV)
FSMC_A[25:0]
td(CLKL-NOEL)
FSMC_NOE
tsu(DV-CLKH)
th(CLKH-DV)
tsu(DV-CLKH)
FSMC_D[15:0]
tsu(NWAITV-CLKH)
FSMC_NWAIT
(WAITCFG = 1b, WAITPOL + 0b)
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
ai14894d
tw(CLK)
BUSTURN = 0
Data latency = 1
td(CLKH-NExH)
td(CLKL-NADVH)
td(CLKH-AIV)
td(CLKH-NOEH)
th(CLKH-DV)
D2
D1
th(CLKH-NWAITV)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
Table 37.
Symbol
t
w(CLK)
t
d(CLKL-NExL)
t
d(CLKH-NExH)
t
d(CLKL-NADVL)
Synchronous non-multiplexed NOR/PSRAM read timings
(1)(2)
Parameter
FSMC_CLK period
FSMC_CLK low to FSMC_NEx low (x = 0...2)
FSMC_CLK high to FSMC_NEx high (x = 0...2)
FSMC_CLK low to FSMC_NADV low
FSMC_CLK low to FSMC_NADV high
FSMC_CLK low to FSMC_Ax valid (x = 0...25)
FSMC_CLK high to FSMC_Ax invalid (x = 0...25) T
HCLK
+ 4
FSMC_CLK low to FSMC_NOE low
FSMC_CLK high to FSMC_NOE high
T
HCLK
+ 1.5
5
0
T
HCLK
+ 2
4
Min
27.7
1.5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
T
HCLK
+ 1.5 ns
ns
ns
ns
ns
ns
t
d(CLKL-NADVH)
t
d(CLKL-AV)
t
d(CLKH-AIV)
t
d(CLKL-NOEL)
t
d(CLKH-NOEH)
t
su(DV-CLKH)
t
h(CLKH-DV)
FSMC_D[15:0] valid data before FSMC_CLK high 6.5
FSMC_D[15:0] valid data after FSMC_CLK high
7
7
2
t
su(NWAITV-CLKH)
FSMC_NWAIT valid before FSMC_SMCLK high
t
h(CLKH-NWAITV)
1. C
L
= 15 pF.
2. Based on characterization, not tested in production.
FSMC_NWAIT valid after FSMC_CLK high
70/123
Doc ID 14611 Rev 7
STMICROELECTRONICS [ STMICROELECTRONICS ]
