STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
Figure 31. Synchronous non-multiplexed PSRAM write timings
tw(CLK)
FSMC_CLK
td(CLKL-NExL)
FSMC_NEx
td(CLKL-NADVL)
FSMC_NADV
td(CLKL-AV)
FSMC_A[25:0]
td(CLKL-NWEL)
FSMC_NWE
td(CLKL-Data)
FSMC_D[15:0]
D1
td(CLKL-Data)
D2
td(CLKH-NWEH)
td(CLKH-AIV)
td(CLKL-NADVH)
Data latency = 1
td(CLKH-NExH)
tw(CLK)
BUSTURN = 0
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
tsu(NWAITV-CLKH)
td(CLKL-NBLH)
th(CLKH-NWAITV)
FSMC_NBL
ai14993e
Table 38.
Symbol
t
w(CLK)
t
d(CLKL-NExL)
t
d(CLKH-NExH)
Synchronous non-multiplexed PSRAM write timings
(1)(2)
Parameter
FSMC_CLK period
FSMC_CLK low to FSMC_NEx low (x = 0...2)
FSMC_CLK high to FSMC_NEx high (x = 0...2)
FSMC_CLK low to FSMC_NADV low
FSMC_CLK low to FSMC_NADV high
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
FSMC_CLK high to FSMC_Ax invalid (x = 16...25)
FSMC_CLK low to FSMC_NWE low
FSMC_CLK high to FSMC_NWE high
FSMC_D[15:0] valid data after FSMC_CLK low
FSMC_NWAIT valid before FSMC_CLK high
FSMC_NWAIT valid after FSMC_CLK high
FSMC_CLK low to FSMC_NBL high
7
2
1
T
HCLK
+ 1
6
T
CK
+ 2
1
5
0
T
HCLK
+ 2
4
Min
27.7
2
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
d(CLKL-NADVL)
t
d(CLKL-NADVH)
t
d(CLKL-AV)
t
d(CLKH-AIV)
t
d(CLKL-NWEL)
t
d(CLKH-NWEH)
t
d(CLKL-Data)
t
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
t
d(CLKL-NBLH)
1. C
L
= 15 pF.
2. Based on characterization, not tested in production.
Doc ID 14611 Rev 7
71/123
STMICROELECTRONICS [ STMICROELECTRONICS ]
