Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms
t
w(NE)
FSMC_NE
t
v(NOE_NE)
t
h(NE_NOE)
FSMC_NOE
t
w(NOE)
FSMC_NWE
t
v(A_NE)
FSMC_A[25:16]
Address
t
h(A_NOE)
t
v(BL_NE)
FSMC_NBL[1:0]
NBL
t
h(BL_NOE)
t
h(Data_NE)
t
su(Data_NE)
t
v(A_NE)
t
su(Data_NOE)
Data
t
h(Data_NOE)
FSMC_AD[15:0]
Address
t
v(NADV_NE)
t
w(NADV)
t
h(AD_NADV)
FSMC_NADV
ai14892b
Table 33.
Symbol
t
w(NE)
t
v(NOE_NE)
t
w(NOE)
t
h(NE_NOE)
t
v(A_NE)
t
v(NADV_NE)
t
w(NADV)
t
h(AD_NADV)
t
h(A_NOE)
t
h(BL_NOE)
t
v(BL_NE)
t
su(Data_NE)
t
h(Data_NE)
t
h(Data_NOE)
1. C
L
= 15 pF.
Asynchronous multiplexed PSRAM/NOR read timings
(1)(2)
Parameter
FSMC_NE low time
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
FSMC_NOE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
FSMC_AD (address) valid hold time after
FSMC_NADV high
Address hold time after FSMC_NOE high
FSMC_BL hold time after FSMC_NOE high
FSMC_NEx low to FSMC_BL valid
Data to FSMC_NEx high setup time
2T
HCLK
+ 24
2T
HCLK
+ 25
0
0
3
T
HCLK
–1.5
T
HCLK
T
HCLK
0
0
Min
7T
HCLK
– 2
4T
HCLK
– 1
–1
0
5
T
HCLK
+ 1.5
Max
7T
HCLK
+ 2
4T
HCLK
+ 2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3T
HCLK
– 0.5 3T
HCLK
+ 1.5
t
su(Data_NOE)
Data to FSMC_NOE high setup time
Data hold time after FSMC_NEx high
Data hold time after FSMC_NOE high
2. Based on characterization, not tested in production.
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