Electrical characteristics
STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
5.3.17
DAC electrical specifications
Table 45. DAC characteristics
Symbol
Parameter
Min Typ Max(1) Unit
Comments
VDDA
Analog supply voltage
2.4
2.4
3.6
V
V
VREF+ must always be below
VDDA
VREF+
Reference supply voltage
3.6
0
VSSA
Ground
0
5
V
(2)
RLOAD
Resistive load with buffer ON
k
When the buffer is OFF, the
Minimum resistive load between
DAC_OUT and VSS to have a
1% accuracy is 1.5 M
(1)
RO
Impedance output with buffer OFF
Capacitive load
15
50
k
Maximum capacitive load at
DAC_OUT pin (when the buffer
is ON).
(1)
CLOAD
pF
V
It gives the maximum output
excursion of the DAC.
DAC_OUT Lower DAC_OUT voltage with buffer
min(1)
ON
0.2
It corresponds to 12-bit input
code (0x0E0) to (0xF1C) at
VREF+ = 3.6 V and (0x155) and
(0xEAB) at VREF+ = 2.4 V
DAC_OUT Higher DAC_OUT voltage with buffer
max(1)
ON
VDDA
0.2
–
V
DAC_OUT Lower DAC_OUT voltage with buffer
min(1)
OFF
0.5
mV
V
It gives the maximum output
excursion of the DAC.
DAC_OUT Higher DAC_OUT voltage with buffer
VREF+
– 1LSB
max(1)
OFF
With no load, worst code
(0xF1C) at VREF+ = 3.6 V in
terms of DC consumption on the
inputs
DAC DC current consumption in
quiescent mode (Standby mode)
IDDVREF+
220
380
480
µA
µA
µA
With no load, middle code
(0x800) on the inputs
DAC DC current consumption in
quiescent mode (Standby mode)
With no load, worst code
(0xF1C) at VREF+ = 3.6 V in
terms of DC consumption on the
inputs
IDDA
Given for the DAC in 10-bit
configuration
0.5
LSB
Differential non linearity Difference
between two consecutive code-1LSB)
DNL(3)
Given for the DAC in 12-bit
configuration
2
1
LSB
LSB
Integral non linearity (difference
between measured value at Code i
and the value at Code i on a line
drawn between Code 0 and last Code
1023)
Given for the DAC in 10-bit
configuration
INL(3)
Given for the DAC in 12-bit
configuration
4
LSB
70/84
Doc ID 16455 Rev 2
STMICROELECTRONICS [ ST ]
