Electrical characteristics
STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
Table 41. ADC characteristics
Symbol
Parameter
Power supply
Conditions
Min
Typ
Max
Unit
VDDA
2.4
2.4
3.6
V
V
VREF+ Positive reference voltage
VDDA
Current on the VREF input
pin
IVREF
160(1) 220(1)
µA
fADC
ADC clock frequency
Sampling rate
0.6
10
1
MHz
MHz
(2)
0.05
fS
fADC = 12 MHz
823
17
kHz
(2)
External trigger frequency
Conversion voltage range
fTRIG
1/fADC
0 (VSSA tied to
ground)
(3)
VREF+
V
VAIN
See Equation 1 and
Table 42 for details
(2)
(2)
RAIN
External input impedance
Sampling switch resistance
50
1
k
k
pF
RADC
Internal sample and hold
capacitor
(2)
8
CADC
f
ADC = 12 MHz
5.9
83
µs
1/fADC
µs
(2)
Calibration time
tCAL
fADC = 12 MHz
fADC = 12 MHz
0.214
3(4)
Injection trigger conversion
latency
(2)
tlat
1/fADC
µs
0.143
2(4)
Regular trigger conversion
latency
(2)
tlatr
1/fADC
µs
0.125
1.5
17.1
239.5
1
(2)
Sampling time
Power-up time
fADC = 12 MHz
tS
1/fADC
µs
(2)
tSTAB
0
0
fADC = 12 MHz
1.17
21
µs
Total conversion time
(including sampling time)
(2)
tCONV
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1. Based on characterization results, not tested in production.
2. Guaranteed by design, not tested in production.
3. In devices delivered in LQFP packages, VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA
Devices that come in the TFBGA64 package have a VREF+ pin but no VREF- pin (VREF- is internally connected to VSSA),
see Table 4: STM32F100xx pin definitions and Figure 6.
.
4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 41.
Equation 1: R
max formula:
AIN
TS
RAIN ------------------------------------------------------------- – RADC
fADC CADC ln2N + 2
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Doc ID 16455 Rev 2
STMICROELECTRONICS [ ST ]
