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STM32F100C8T6BTR 参数 Datasheet PDF下载

STM32F100C8T6BTR图片预览
型号: STM32F100C8T6BTR
PDF下载: 下载PDF文件 查看货源
内容描述: 低和中等密度值线,先进的基于ARM的32位MCU低和中等密度值线,先进的基于ARM的32位MCU [Low & medium-density value line, advanced ARM-based 32-bit MCU Low & medium-density value line, advanced ARM-based 32-bit MCU]
分类和应用:
文件页数/大小: 84 页 / 1148 K
品牌: STMICROELECTRONICS [ ST ]
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STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB  
Electromagnetic Interference (EMI)  
Electrical characteristics  
The electromagnetic field emitted by the device is monitored while a simple application is  
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with  
IEC 61967-2 standard which specifies the test board and the pin loading.  
Table 30. EMI characteristics  
Max vs. [fHSE/fHCLK  
]
Monitored  
frequency band  
Symbol Parameter  
Conditions  
Unit  
8/24 MHz  
0.1 MHz to 30 MHz  
30 MHz to 130 MHz  
130 MHz to 1GHz  
SAE EMI Level  
9
17  
16  
4
VDD 3.3 V, TA 25°C,  
LQFP100 package  
compliant with  
dBµV  
-
SEMI  
Peak level  
IEC 61967-2  
5.3.11  
Absolute maximum ratings (electrical sensitivity)  
Based on three different tests (ESD, LU) using specific measurement methods, the device is  
stressed in order to determine its performance in terms of electrical sensitivity.  
Electrostatic discharge (ESD)  
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are  
applied to the pins of each sample according to each pin combination. The sample size  
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test  
conforms to the JESD22-A114/C101 standard.  
Table 31. ESD absolute maximum ratings  
Maximum  
Symbol  
Ratings  
Conditions  
Class  
Unit  
value(1)  
Electrostatic discharge  
voltage (human body model) conforming to JESD22-A114  
TA +25 °C  
VESD(HBM)  
2
II  
TBD  
V
Electrostatic discharge TA +25 °C  
voltage (charge device model) conforming to JESD22-C101  
VESD(CDM)  
TBD  
1. Based on characterization results, not tested in production.  
Static latch-up  
Two complementary static tests are required on six parts to assess the latch-up  
performance:  
A supply overvoltage is applied to each power supply pin  
A current injection is applied to each input, output and configurable I/O pin  
These tests are compliant with EIA/JESD78 IC latch-up standard.  
Table 32. Electrical sensitivities  
Symbol  
Parameter  
Conditions  
Class  
LU  
Static latch-up class  
TA +105 °C conforming to JESD78  
TBD  
Doc ID 16455 Rev 2  
53/84  
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