STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
Output voltage levels
Electrical characteristics
Unless otherwise specified, the parameters given in Table 34 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 8. All I/Os are CMOS and TTL compliant.
Table 34. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max Unit
Output Low level voltage for an I/O pin
when 8 pins are sunk at the same time
(1)
0.4
V
VOL
TTL port,
IIO = +8 mA,
2.7 V < VDD < 3.6 V
Output High level voltage for an I/O pin
when 8 pins are sourced at the same time
(2)
VDD–0.4
VOH
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
(1)
0.4
V
VOL
CMOS port
IIO = +8 mA
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
(2)
2.7 V < VDD < 3.6 V
2.4
VOH
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
(1)
1.3
V
VOL
I
IO = +20 mA(3)
2.7 V < VDD < 3.6 V
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
(2)
VDD–1.3
VOH
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
(1)
0.4
V
VOL
IIO = +6 mA(3)
2 V < VDD < 2.7 V
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
(2)
VDD–0.4
VOH
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 6
and the sum of IIO (I/O ports and control pins) must not exceed IVSS
.
2. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 6 and the sum of IIO (I/O ports and control pins) must not exceed IVDD
.
3. Based on characterization data, not tested in production.
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