Applicative block diagrams
STM32F105xx, STM32F107xx
Figure 43. RMII with a 50 MHz oscillator
Ethernet
PHY 10/100
STM32F107xx
MCU
RMII_TX_EN
Ethernet
MAC 10/100
RMII_TXD[1:0]
RMII_RXD[1:0]
RMII_CRX_DV
RMII_REF_CLK
RMII
= 7 pins
HCLK(1)
RMII + MDC
= 9 pins
IEEE1588 PTP
MDIO
MDC
Timer
input
trigger
Timestamp
comparator
TIM2
/2 or /20
2.5 or 25 MHz
50 MHz
synchronous
HCLK
PLL
OSC
50 MHz
PHY_CLK 50 MHz XT1
50 MHz
ai15657
1. HCLK must be greater than 25 MHz.
Figure 44. RMII with a 25 MHz crystal and PHY with PLL
STM32F107xx
Ethernet
PHY 10/100
MCU
RMII_TX_EN
Ethernet
MAC 10/100
RMII_TXD[1:0]
RMII_RXD[1:0]
RMII
= 7 pins
HCLK(1)
RMII_CRX_DV
REF_CLK
RMII + MDC
= 9 pins
RMII_REF_CLK
IEEE1588 PTP
MDIO
Timer
input
trigger
MDC
Timestamp
comparator
TIM2
/2 or /20
synchronous
2.5 or 25 MHz
OSC
50 MHz
PLL
XT1
HCLK
XTAL
25 MHz
PLL
PHY_CLK 25 MHz
ai15658
1. HCLK must be greater than 25 MHz.
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Doc ID 15274 Rev 4
STMICROELECTRONICS [ ST ]
