STM32F105xx, STM32F107xx
Applicative block diagrams
Figure 41. OTG connection (any protocol)
STM32F105xx/STM32F107xx
OTG PHY
DP
USB
full-speed/
low-speed
transceiver
DM
ID
USB
OTG
Full-speed
core
HNP
ID
V
BUS
V
SS
(2)
DD
V
SRP
Current-limited
power distribution
switch
STMPS2141STR(1)
EN
5 V
GPIO
GPIO + IRQ
OVRCR
flag
ai15655b
1. STMPS2141STR needed only if the application has to support bus-powered devices.
2. VDD ranges between 2 V and 3.6 V.
A.2
Ethernet interface solutions
Figure 42. MII mode using a 25 MHz crystal
STM32F107xx
MII_TX_CLK
MII_TX_EN
MCU
Ethernet
MAC 10/100
Ethernet
PHY 10/100
MII_TXD[3:0]
MII_CRS
MII
= 15 pins
MII_COL
HCLK(1)
MII_RX_CLK
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
MII + MDC
= 17 pins
IEEE1588 PTP
Timer
input
trigger
Timestamp
comparator
MDIO
MDC
TIM2
PPS_OUT(2)
HCLK
PLL
XTAL
25 MHz
OSC
PHY_CLK 25 MHz
XT1
ai15656
1. HCLK must be greater than 25 MHz.
2. Pulse per second when using IEEE1588 PTP, optional signal.
Doc ID 15274 Rev 4
85/95
STMICROELECTRONICS [ ST ]
