Description
STM32F405xx, STM32F407xx
2.2
Device overview
Figure 5. STM32F40x block diagram
External memory
controller (FSMC)
SRAM, PSRAM, NOR Flash,
PC Card (ATA), NAND Flash
CLK, NE [3:0], A[23:0],
D[31:0], OEN, WEN,
NBL[3:0], NL, NREG,
NWAIT/IORDY, CD
CCM data RAM 64 KB
NJTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
AHB3
JTAG & SW
ETM
MPU
NVIC
NIORD, IOWR, INT[2:3]
INTN, NIIS16 as AF
TRACECLK
TRACED[3:0]
D-BUS
ARM Cortex-M4
168 MHz
FPU
I-BUS
Flash
up to
1 MB
S-BUS
RNG
DMA/
FIFO
Ethernet MAC
10/100
MII or RMII as AF
MDIO as AF
HSYNC, VSYNC
PUIXCLK, D[13:0]
Camera
interface
SRAM 112 KB
SRAM 16 KB
USB
OTG HS
DMA/
FIFO
DP, DM
ULPI:CK, D[7:0], DIR, STP, NXT
ID, VBUS, SOF
DP
USB
DM
OTG FS
8 Streams
FIFO
ID, VBUS, SOF
AHB2 168 MHz
DMA2
DMA1
AHB1 168 MHz
8 Streams
FIFO
Power managmt
VDD
Voltage
regulator
VDD = 1.8 to 3.6 V
VSS
3.3 to 1.2 V
VCAP1, VCPA2
@VDD
@VDDA
POR
reset
Supply
supervision
RC HS
PA[15:0]
PB[15:0]
PC[15:0]
GPIO PORT A
GPIO PORT B
GPIO PORT C
RC LS
P LL1&2
POR/PDR
Int
VDDA, VSSA
NRST
BOR
PVD
@VDD
@VDDA
PD[15:0]
PE[15:0]
GPIO PORT D
GPIO PORT E
GPIO PORT F
GPIO PORT G
GPIO PORT H
GPIO PORT I
OSC_IN
OSC_OUT
XTAL OSC
4- 16MHz
Reset &
IWDG
clock
M AN A G T
control
PF[15:0]
PG[15:0]
PWR
VBAT = 1.65 to 3.6 V
interface
@VBAT
OSC32_IN
OSC32_OUT
PH[15:0]
PI[11:0]
XTAL 32 kHz
RTC
AWU
Backup register
RTC_AF1
RTC_AF1
4 KB BKPSRAM
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
4 channels
32b
TIM2
16b
TIM3
140 AF
EXT IT. WKUP
SDIO / MMC
16b
TIM4
DMA2
DMA1
32b
TIM5
D[7:0]
CMD, CK as AF
AHB/APB2 AHB/APB1
16b
2 channels as AF
1 channel as AF
TIM12
4 compl. channels (TIM1_CH1[1:4]N,
4 channels (TIM1_CH1[1:4]ETR,
BKIN as AF
16b
16b
TIM1 / PWM
TIM8 / PWM
TIM13
4 compl. channels (TIM1_CH1[1:4]N,
4 channels (TIM1_CH1[1:4]ETR,
BKIN as AF
1 channel as AF
16b
TIM14
16b
RX, TX as AF
CTS, RTS as AF
smcard
USART2
irDA
2 channels as AF
16b
16b
16b
TIM9
TIM10
TIM11
RX, TX as AF
CTS, RTS as AF
smcard
USART3
irDA
1 channel as AF
1 channel as AF
RX, TX as AF
RX, TX as AF
UART4
UART5
WWDG
smcard
RX, TX, CK,
CTS, RTS as AF
RX, TX, CK,
CTS, RTS as AF
MOSI, MISO,
SCK, NSS as AF
USART1
USART6
SPI1
MOSI/SD, MISO/SD_ext, SCK/CK
NSS/WS, MCK as AF
irDA
SP2/I2S2
SP3/I2S3
I2C1/SMBUS
I2C2/SMBUS
I2C3/SMBUS
bxCAN1
smcard
irDA
16b
16b
MOSI/SD, MISO/SD_ext, SCK/CK
NSS/WS, MCK as AF
TIM6
TIM7
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
TX, RX
@VDDA
VDDREF_ADC
@VDDA
Temperature sensor
ADC1
8 analog inputs common
to the 3 ADCs
DAC1
DAC2
ITF
8 analog inputs common
to the ADC1 & 2
IF
ADC2
ADC3
TX, RX
bxCAN2
8 analog inputs for ADC3
DAC1_OUT
as AF
DAC2_OUT
as AF
MS19920V3
1. The timers connected to APB2 are clocked from TIMxCLK up to 168 MHz, while the timers connected to
APB1 are clocked from TIMxCLK either up to 84 MHz or 168 MHz, depending on TIMPRE bit configuration
in the RCC_DCKCFGR register.
2. The camera interface and ethernet are available only on STM32F407xx devices.
18/185
DocID022152 Rev 4
STMICROELECTRONICS [ ST ]
