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STM32F107VCT6TR 参数 Datasheet PDF下载

STM32F107VCT6TR图片预览
型号: STM32F107VCT6TR
PDF下载: 下载PDF文件 查看货源
内容描述: [Mainstream Connectivity line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, Ethernet MAC, CAN and USB 2.0 OTG]
分类和应用: 闪存
文件页数/大小: 103 页 / 1881 K
品牌: STMICROELECTRONICS [ ST ]
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Electrical characteristics  
STM32F105xx, STM32F107xx  
Electromagnetic Interference (EMI)  
The electromagnetic field emitted by the device are monitored while a simple application is  
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with SAE  
IEC61967-2 standard which specifies the test board and the pin loading.  
Table 32. EMI characteristics  
Max vs. [fHSE/fHCLK  
]
Monitored  
Symbol  
Parameter  
Conditions  
Unit  
frequency band  
8/48 MHz  
8/72 MHz  
0.1 to 30 MHz  
30 to 130 MHz  
130 MHz to 1GHz  
SAE EMI Level  
9
26  
25  
4
9
13  
31  
4
VDD = 3.3 V, TA = 25 °C,  
Peak level LQFP100 package  
dBµV  
-
SEMI  
compliant with IEC61967-2  
5.3.11  
Absolute maximum ratings (electrical sensitivity)  
Based on three different tests (ESD, LU) using specific measurement methods, the device is  
stressed in order to determine its performance in terms of electrical sensitivity.  
Electrostatic discharge (ESD)  
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are  
applied to the pins of each sample according to each pin combination. The sample size  
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test  
conforms to the JESD22-A114/C101 standard.  
Table 33. ESD absolute maximum ratings  
Symbol  
Ratings  
Conditions  
Class Maximum value(1) Unit  
Electrostatic discharge voltage TA = +25 °C conforming to  
(human body model) JESD22-A114  
VESD(HBM)  
2
2000  
500  
V
Electrostatic discharge voltage TA = +25 °C conforming to  
(charge device model) JESD22-C101  
VESD(CDM)  
II  
1. Based on characterization results, not tested in production.  
Static latch-up  
Two complementary static tests are required on six parts to assess the latch-up  
performance:  
A supply overvoltage is applied to each power supply pin  
A current injection is applied to each input, output and configurable I/O pin  
These tests are compliant with EIA/JESD 78A IC latch-up standard.  
Table 34. Electrical sensitivities  
Symbol  
Parameter  
Conditions  
Class  
LU  
Static latch-up class  
TA = +105 °C conforming to JESD78A  
II level A  
54/104  
Doc ID 15274 Rev 6  
 
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