Electrical characteristics
STM32F105xx, STM32F107xx
Table 36. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Standard IO Schmitt
trigger voltage
hysteresis(2)
200
mV
Vhys
IO FT Schmitt trigger
voltage hysteresis(2)
(3)
5% VDD
mV
µA
VSS ≤ VIN ≤ VDD
Standard I/Os
±1
Ilkg
Input leakage current (4)
VIN= 5 V, I/O FT
3
All pins
except for
PA10
Weak pull-
up
30
8
40
11
40
50
15
50
15
RPU
VIN = VSS
kΩ
equivalent
resistor(5)
PA10
All pins
except for
PA10
Weak pull-
down
30
8
RPD
VIN = VDD
kΩ
equivalent
resistor(5)
PA10
11
5
CIO
I/O pin capacitance
pF
1. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be
disabled.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 18 and Figure 19 for standard I/Os, and
in Figure 20 and Figure 21 for 5 V tolerant I/Os.
Figure 18. Standard I/O input characteristics - CMOS port
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Doc ID 15274 Rev 6
STMICROELECTRONICS [ ST ]
