STM32F105xx, STM32F107xx
Electrical characteristics
All timings are derived from tests performed under ambient temperature and V supply
DD
voltage conditions summarized in Table 9.
Table 26. Low-power mode wakeup timings
Symbol
Parameter
Wakeup from Sleep mode
Typ
Unit
(1)
1.8
µs
tWUSLEEP
Wakeup from Stop mode (regulator in run mode)
3.6
5.4
(1)
µs
µs
tWUSTOP
Wakeup from Stop mode (regulator in low power mode)
(1)
Wakeup from Standby mode
50
tWUSTDBY
1. The wakeup times are measured from the wakeup event to the point in which the user application code
reads the first instruction.
5.3.8
PLL, PLL2 and PLL3 characteristics
The parameters given in Table 27 and Table 28 are derived from tests performed under
temperature and V supply voltage conditions summarized in Table 9.
DD
Table 27. PLL characteristics
Symbol
Parameter
Min(1)
Max(1)
Unit
PLL input clock(2)
3
12
MHz
ns
fPLL_IN
Pulse width at high level
PLL multiplier output clock
PLL VCO output
30
18
36
fPLL_OUT
fVCO_OUT
tLOCK
72
MHz
MHz
µs
144
350
300
PLL lock time
Jitter
Cycle-to-cycle jitter
ps
1. Based on characterization, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT
.
Table 28. PLL2 and PLL3 characteristics
Symbol Parameter
PLL input clock(2)
Min(1)
Max(1)
Unit
3
5
MHz
ns
fPLL_IN
Pulse width at high level
PLL multiplier output clock
PLL VCO output
30
40
80
fPLL_OUT
fVCO_OUT
tLOCK
74
MHz
MHz
µs
148
350
400
PLL lock time
Jitter
Cycle-to-cycle jitter
ps
1. Based on characterization, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT
.
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