STM32F103xC, STM32F103xD, STM32F103xE
I2S - SPI characteristics
Electrical characteristics
2
Unless otherwise specified, the parameters given in Table 51 for SPI or in Table 52 for I S
are derived from tests performed under ambient temperature, f
frequency and V
PCLKx
DD
supply voltage conditions summarized in Table 9.
Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate
2
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I S).
(1) (2)
Table 51. SPI characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
Master mode
Slave mode
0
0
18
18
fSCK
1/tc(SCK)
SPI clock frequency
MHz
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
8
(3)
tsu(NSS)
NSS setup time
NSS hold time
Slave mode
Slave mode
tC(SCK)
(3)
th(NSS)
0.5tC(SCK)
(3)
tw(SCKH)
tw(SCKL)
SCK high and low time Master mode, fPCLK = 36 MHz, presc = 4
50
60
(3)
(3)
Master mode
Data input setup time
10
tsu(MI)
tsu(SI)
(3)
Slave mode
5
Master mode, fPCLK = 36 MHz, presc = 4
15
(3)
Slave mode, fPCLK = 36 MHz, presc = 4
Data input hold time
5
th(MI)
th(SI)
(3)
Master mode, fPCLK = TBD
TBD(4)
Slave mode, fPCLK = TBD
TBD(4)
ns
Slave mode, fPCLK = 36 MHz, presc = 4
Data output access time
0
0
5
60
(3)(5)
(3)(6)
ta(SO)
Slave mode, fPCLK = TBD
TBD
TBD
tdis(SO)
Data output disable time Slave mode
Slave mode (after enable edge),
fPCLK = 36 MHz, presc = 4
Data output valid time
30
TBD
10
(3)(1)
tv(SO)
fPCLK = TBD
Master mode (after enable edge),
fPCLK = 36 MHz, presc = 4
(3)(1)
(3)
tv(MO)
Data output valid time
fPCLK = TBD
TBD
30
TBD
th(SO)
Slave mode (after enable edge)
Data output hold time
(3)
th(MO)
Master mode (after enable edge)
10
1. TBD = to be determined.
2. Remapped SPI1 characteristics to be determined.
3. Values based on design simulation and/or characterization results, and not tested in production.
4. Depends on fPCLK. For example, if fPCLK= 8MHz, then tPCLK = 1/fPLCLK =125 ns and tv(MO) = 255 ns.
5. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
6. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z
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