Electrical characteristics
Table 52.
Symbol
f
CK
1/t
c(CK)
t
r(CK)
t
f(CK)
t
v(WS) (2)
t
h(WS) (2)
t
su(WS) (2)
t
h(WS) (2)
t
w(CKH) (2)
t
w(CKL) (2)
t
su(SD_MR) (2)
t
su(SD_SR) (2)
t
h(SD_MR)(2)(3)
t
h(SD_SR) (2)(3)
t
h(SD_MR)
t
h(SD_SR) (2)
STM32F103xC, STM32F103xD, STM32F103xE
I
2
S characteristics
(1)
Parameter
I
2
S clock frequency
I
2
S clock rise and fall time
WS valid time
WS hold time
WS setup time
WS hold time
CK high and low time
Data input setup time
Data input hold time
Data input hold time
Conditions
Master
Slave
capacitive load
C
L
= 50 pF
Master
Master
Slave
Slave
Master f
PCLK
= TBD,
presc = TBD
Master receiver
Slave receiver
Master receiver
Slave receiver
Master f
PCLK
= TBD
Slave f
PCLK
= TBD
Slave transmitter
(after enable edge)
f
PCLK
= TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Min
TBD
0
Max
TBD
MHz
TBD
TBD
Unit
ns
t
v(SD_ST) (2)(3)
Data output valid time
t
h(SD_ST) (2)
Data output hold time
Slave transmitter
(after enable edge)
Master transmitter
(after enable edge)
f
PCLK
= TBD
t
v(SD_MT)
Data output valid time
t
h(SD_MT) (2)
Data output hold time
Master transmitter
(after enable edge)
1. TBD = to be determined.
2. Data based on design simulation and/or characterization results, not tested in production.
3. Depends on f
PCLK
. For example, if f
PCLK
=8 MHz, then T
PCLK
= 1/f
PLCLK
=125 ns.
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