STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
2
(1)
Figure 46. I S slave timing diagram
t
c(CK)
CPOL = 0
CPOL = 1
t
t
t
w(CKL)
h(WS)
w(CKH)
WS input
t
t
t
h(SD_ST)
t
v(SD_ST)
su(WS)
SD
transmit
MSB transmit
MSB receive
Bitn transmit
LSB transmit
t
su(SD_SR)
h(SD_SR)
Bit1 receive
LSB receive
SD
receive
ai14881
1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD
.
2
(1)
Figure 47. I S master timing diagram
t
t
f(CK)
r(CK)
t
c(CK)
CPOL = 0
t
w(CKH)
CPOL = 1
t
t
t
v(WS)
h(WS)
w(CKL)
WS output
t
t
h(SD_MT)
t
v(SD_MT)
su(SD_MR)
SD
receive
MSB receive
Bitn receive
LSB receive
t
h(SD_MR)
Bitn transmit
MSB transmit
LSB transmit
SD
transmit
ai14884
1. Data based on design simulation and/or characterization results, not tested in production.
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