Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Figure 41. Recommended NRST pin protection
V
DD
External
reset circuit
R
PU
Internal Reset
NRST
FILTER
0.1 µF
STM32F101xx
ai14132b
5. The reset network protects the device against parasitic resets.
6. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 47. Otherwise the reset will not be taken into account by the device.
5.3.15
TIM timer characteristics
The parameters given in Table 48 are guaranteed by fabrication.
Refer to Section 5.3.13: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)
Table 48. TIMx characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
tTIMxCLK
ns
1
tres(TIM)
Timer resolution time
fTIMxCLK = 72 MHz 13.9
0
fTIMxCLK/2
36
MHz
Timer external clock
frequency on CH1 to CH4
fEXT
fTIMxCLK = 72 MHz
0
MHz
ResTIM
Timer resolution
16
bit
16-bit counter clock period
when internal clock is
selected
tTIMxCLK
1
65536
tCOUNTER
fTIMxCLK = 72 MHz 0.0139
910
µs
tTIMxCLK
s
65536 × 65536
59.6
tMAX_COUNT
Maximum possible count
fTIMxCLK = 72 MHz
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.
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