STLC60135
121
123
124
125
126
128
129
130
132
133
135
136
138
139
140
142
143
PDOWN
AFRXD_0
AFRXD_1
AFRXD_2
AFRXD_3
CLWD
O
I
Table 6: (continued)
Sequence
Number
Mnemonic
Pin BS Type
I
I
61
U_TxRefB
U_RxCLK
I
I
63
1
1
1
I
64
U_RxSOC
MCLK
C
O
O
O
O
O
none
O
O
O
O
65
U_RxCLAV
U_RxENBB
U_TxCLK
CTRLDATA
AFTXED_0
AFTXED_0
AFTXED_0
AFTXED_0
IDDq
66
68
69
U_TxSOC
70
U_TxCLAV
71
U_TxENBB
U_TxData_7
U_TxData_6
U_TxData_5
U_TxData_4
U_TxData_3
U_TxData_2
U_TxData_1
U_TxData_0
U_TxADDR_4
U_TxADDR_3
U_TxADDR_2
U_TxADDR_1
U_TxADDR_0
SLR_FRAME_F
SLR_FRAME_S
SLR_DATA_S_1
SLR_DATA_S_0
SLR_DATA_S
SLR_DATA_F_1
SLR_DATA_F_0
SLR_VAL_F
SLAP_CLOCK
SLT_FRAME_F
SLT_DATA_F_1
SLT_DATA_F_0
SLT_DATA_S_1
SLT_DATA_S_0
SLT_REQ_F
SLT_REQ_S
SLT_FRAME_S
TDI
74
I
I
I
I
I
I
I
I
I
I
I
I
I
AFTXD_0
AFTXD_1
AFTXD_0
AFTXD_1
75
77
78
79
80
General purpose I/O register
2 generalPurpose Register (0x040)
82
83
84
Position Length
bits
Field
Type
Function
85
87
GP_IN
R
[0,1]
2
1
Sampled level
on pins GP_IN
88
89
GP_OUT RW
[2]
Output level on
pins GP_OUT
90
92
bits from 3 to 15 are reserved
93
94
Reset Initialization
96
The STLC60135 supports two reset modes:
97
- A ’hardware’ reset is activated by the RESETB
pin (active low). A hard reset occurs when a low
input value is detected at the RESETB input.
The low level must be applied for at least 1ms
to guarantee a correct reset operation. All
clocks and power supplies must be stable for
200ns prior to the rising edge of the RESETB
signal.
- ’Soft’ reset activated by the controller write ac-
cess to a soft reset configuration bit. The reset
process takes less than 10000 MCLK clock cy-
cles.
98
99
100
101
103
104
105
106
107
110
111
112
113
114
116
118
119
120
ELECTRICAL SPECIFICATIONS
Generic
The values presented in the following table apply
for all inputs and/or outputs unless specified oth-
erwise. Specifically they are not influenced by the
choice between CMOS or TTL levels.
TDO
TMS
TCK
TRSTB
TESTSE
none
O
GP_OUT
22/25
STMICROELECTRONICS [ ST ]
