Register description
STA335BW
5.1.3
Thermal warning recovery bypass
Bit
R/W
RST
Name
Description
0 – Thermal warning Recovery enabled
1 – Thermal warning Recovery disabled
5
R/W
1
TWRB
If the thermal warning adjustment is enabled(TWAB=0), then the thermal warning recovery
determines if the -3 dB output limit is removed when thermal warning is negative.
If TWRB=0 and TWAB=0, then when a thermal warning disappears the -3 dB output limit is
removed and the gain is added back to the system. If TWRB=1 and TWAB=0, then when a
thermal warning disappears the -3 dB output limit remains until TWRB is changed to zero or
the device is reset.
5.1.4
Thermal warning adjustment bypass
Bit
R/W
RST
Name
Description
0 – Thermal warning adjustment enabled
1 – Thermal warning adjustment disabled
6
R/W
1
TWAB
The on-chip STA335BW power output block provides feedback to the digital controller using
inputs to the power control block. The TWARN input is used to indicate a thermal warning
condition. When TWARN is asserted (set to 0) for a period of time greater than 400 ms, the
power control block forces a -3 dB output limit (determined by TWOCL in Coeff RAM) to the
modulation limit in an attempt to eliminate the thermal warning condition. Once the thermal
warning output limit adjustment is applied, it remains in this state until reset, unless
FDRB = 0.
5.1.5
Fault detect recovery bypass
Bit
R/W
RST
Name
Description
0 – Fault Detect Recovery enabled
1 – Fault Detect Recovery disabled
7
R/W
0
FDRB
The on-chip STA335BW power output block provides feedback to the digital controller using
inputs to the Power Control block. The FAULT input is used to indicate a fault condition
(either over-current or thermal). When FAULT is asserted (set to 0), the power control block
attempts a recovery from the fault by asserting the tri-state output (setting it to 0 which
directs the power output block to begin recovery), holds it at 0 for period of time in the range
of 0.1 ms to 1 second as defined by the Fault-Detect Recovery Constant register (FDRC
registers 29-2Ah), then toggles it back to 1. This sequence is repeated as log as the fault
indication exists. This feature is enabled by default but can be bypassed by setting the
FDRB control bit to 1.
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STMICROELECTRONICS [ ST ]
