Register description
STA335BW
D0
Table 7.
Addr
Register summary (continued)
Name
D7
D6
D5
D4
D3
D2
D1
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
A2cf1
A2cf2
C4B23
C4B15
C4B7
C4B22
C4B14
C4B6
C4B21
C4B13
C4B5
C4B20
C4B12
C4B4
C4B19
C4B11
C4B3
C5B19
C5B11
C5B3
RA
C4B18
C4B10
C4B2
C5B18
C5B10
C5B2
R1
C4B17
C4B9
C4B1
C5B17
C5B9
C5B1
WA
C4B16
C4B8
C4B0
C5B16
C5B8
C5B0
W1
A2cf3
B0cf1
C5B23
C5B15
C5B7
C5B22
C5B14
C5B6
C5B21
C5B13
C5B5
C5B20
C5B12
C5B4
B0cf2
B0cf3
Cfud
MPCC1
MPCC2
DCC1
MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8
MPCC7 MPCC6
MPCC5
DCC13
DCC5
MPCC4
DCC12
DCC4
MPCC3
DCC11
DCC3
MPCC2
DCC10
DCC2
MPCC1 MPCC0
DCC15
DCC7
DCC14
DCC6
DCC9
DCC1
DCC8
DCC0
DCC2
FDRC1
FDRC2
Status
reserved
reserved
reserved
FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10
FDRC9
FDRC1
FDRC8
FDRC0
FDRC7
PLLUL
FDRC6
FAULT
FDRC5
FDRC4
FDRC3
FDRC2
UVFAULT OVFAULT OCFAULT OCWARN TFAULT TWARN
RO1BACT R5BACT R4BACT R3BACT R2BACT R1BACT
R01BEND R5BEND R4BEND R3BEND R2BEND R1BEND
R5BBAD R4BBAD R3BBAD R2BBAD R1BBAD
5.1
Configuration register A (address 0x00)
D7
D6
D5
D4
D3
D2
D1
D0
FDRB
0
TWAB
1
TWRB
1
IR1
0
IR0
0
MCS2
0
MCS1
1
MCS0
1
5.1.1
Master clock select
Bit
R/W
RST
Name
Description
0
1
2
R/W
R/W
R/W
1
1
0
MCS0
MCS1
MCS2
Selects the ratio between the input I2S sample
frequency and the input clock.
The STA335BW supports sample rates of 32 KHz, 44.1 KHz, 48 KHz, 88.2 KHz, 96 KHz,
176.4 KHz, and 192 KHz. Therefore the internal clock is:
●
●
●
32.768 MHz for 32 KHz
45.1584 MHz for 44.1 KHz, 88.2 KHz, and 176.4 KHz
49.152 MHz for 48 KHz, 96 KHz, and 192 KHz
18/54
STMICROELECTRONICS [ ST ]
