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ST92F150JDV1Q6 参数 Datasheet PDF下载

ST92F150JDV1Q6图片预览
型号: ST92F150JDV1Q6
PDF下载: 下载PDF文件 查看货源
内容描述: 8月16日- BIT单电压闪存单片机系列内存, E3 TMEMULATED EEPROM , CAN 2.0B和J1850 BLPD [8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TMEMULATED EEPROM, CAN 2.0B AND J1850 BLPD]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 426 页 / 3830 K
品牌: STMICROELECTRONICS [ ST ]
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ST92F124/F150/F250 - INTERRUPTS  
Figure 45. Example of Dynamic Priority  
Level Modification in Nested Mode  
– The PC low byte is pushed onto system stack.  
– The PC high byte is pushed onto system stack.  
INTERRUPT 6 HAS PRIORITY LEVEL 6  
Priority Level  
– If ENCSR is set, CSR is pushed onto system  
stack.  
CPL is set to 7  
by MAIN program  
4
– The Flag register is pushed onto system stack.  
ei  
INT6  
– The PC is loaded with the 16-bit vector stored in  
the Vector Table, pointed to by the IVR.  
5
6
7
MAIN  
CPL is set to 5  
– If ENCSR is set, CSR is loaded with ISR con-  
tents; otherwise ISR is used in place of CSR until  
iretinstruction.  
CPL6 > CPL5:  
INT6 pending  
INT 6  
CPL=6  
End of Interrupt Routine  
The Interrupt Service Routine must be ended with  
the iret instruction. The iret instruction exe-  
cutes the following operations:  
MAIN  
CPL=7  
– The Flag register is popped from system stack.  
5.5 ARBITRATION MODES  
– If ENCSR is set, CSR is popped from system  
stack.  
The ST9 provides two interrupt arbitration modes:  
Concurrent mode and Nested mode. Concurrent  
mode is the standard interrupt arbitration mode.  
Nested mode improves the effective interrupt re-  
sponse time when service routine nesting is re-  
quired, depending on the request priority levels.  
– The PC high byte is popped from system stack.  
– The PC low byte is popped from system stack.  
– All unmasked Interrupts are enabled by setting  
the CICR.IEN bit.  
The IAM control bit in the CICR Register selects  
Concurrent Arbitration mode or Nested Arbitration  
Mode.  
– If ENCSR is reset, CSR is used instead of ISR.  
Normal program execution thus resumes at the in-  
terrupted instruction. All pending interrupts remain  
pending until the next ei instruction (even if it is  
executed during the interrupt service routine).  
5.5.1 Concurrent Mode  
This mode is selected when the IAM bit is cleared  
(reset condition). The arbitration phase, performed  
during every instruction, selects the request with  
the highest priority level. The CPL value is not  
modified in this mode.  
Note: In Concurrent mode, the source priority level  
is only useful during the arbitration phase, where it  
is compared with all other priority levels and with  
the CPL. No trace is kept of its value during the  
ISR. If other requests are issued during the inter-  
rupt service routine, once the global CICR.IEN is  
re-enabled, they will be acknowledged regardless  
of the interrupt service routine’s priority. This may  
cause undesirable interrupt response sequences.  
Start of Interrupt Routine  
The interrupt cycle performs the following steps:  
– All maskable interrupt requests are disabled by  
clearing CICR.IEN.  
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