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ST92F150JDV1Q6 参数 Datasheet PDF下载

ST92F150JDV1Q6图片预览
型号: ST92F150JDV1Q6
PDF下载: 下载PDF文件 查看货源
内容描述: 8月16日- BIT单电压闪存单片机系列内存, E3 TMEMULATED EEPROM , CAN 2.0B和J1850 BLPD [8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TMEMULATED EEPROM, CAN 2.0B AND J1850 BLPD]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 426 页 / 3830 K
品牌: STMICROELECTRONICS [ ST ]
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CONTROLLER AREA NETWORK (bxCAN)  
CONTROLLER AREA NETWORK (Cont’d)  
10.10.5.2 Time Triggered Communication  
Mode  
completely by hardware. The application accesses  
the messages stored in the FIFO through the FIFO  
output mailbox.  
In this mode, the internal counter of the CAN hard-  
ware is activated and used to generate the Time  
Stamp value stored in the MTSRH and MTSRL  
registers. The internal counter is captured on the  
sample point of the Start Of Frame bit in both re-  
ception and transmission.  
Valid Message  
A received message is considered as valid when it  
has been received correctly according to the CAN  
protocol (no error until the last but one bit of the  
EOF field) and It passed through the identifier fil-  
tering successfully, see Section 10.10.5.4 Identifi-  
er Filtering.  
10.10.5.3 Reception Handling  
For the reception of CAN messages, three  
mailboxes organized as a FIFO are provided. In  
order to save CPU load, simplify the software and  
guarantee data consistency, the FIFO is managed  
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