CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
FIFO Management
On overrun condition, the FOVR bit is set and an
interrupt is generated if the FOVIE bit in the CIER
register is set.
Starting from the empty state, the first valid mes-
sage received is stored in the FIFO which be-
comes pending_1. The hardware signals the
event setting the FMP[1:0] bits in the CRFR regis-
ter to the value 01b. The message is available in
the FIFO output mailbox. The software reads out
the mailbox content and releases it by setting the
RFOM bit in the CRFR register. The FIFO be-
comes empty again. If a new valid message has
been received in the meantime, the FIFO stays in
pending_1 state and the new message is availa-
ble in the output mailbox.
10.10.5.4 Identifier Filtering
In the CAN protocol the identifier of a message is
not associated with the address of a node but re-
lated to the content of the message. Consequently
a transmitter broadcasts its message to all receiv-
ers. On message reception a receiver node de-
cides - depending on the identifier value - whether
the software needs the message or not. If the mes-
sage is needed, it is copied into the RAM. If not,
the message must be discarded without interven-
tion by the software.
If the application does not release the mailbox, the
next valid message will be stored in the FIFO
which enters pending_2 state (FMP[1:0] = 10b).
The storage process is repeated for the next valid
message putting the FIFO into pending_3 state
(FMP[1:0] = 11b). At this point, the software must
release the output mailbox by setting the RFOM
bit, so that a mailbox is free to store the next valid
message. Otherwise the next valid message re-
ceived will cause a loss of message.
To fulfil this requirement, the bxCAN Controller
provides eight configurable and scalable filter-
banks (0-7) to the application, in order to receive
only the messages the software needs. This hard-
ware filtering saves CPU resources which would
be otherwise needed to perform filtering by soft-
ware. Each filter bank consists of eight 8-bit regis-
ters, CFxR[0:7].
Scalable Width
Refer also to Section 10.10.5.5 Message Storage
To optimize and adapt the filters to the application
needs, each filter bank can be scaled independ-
ently. Depending on the filter scale a filter bank
provides:
Overrun
Once the FIFO is in pending_3 state (i.e. the three
mailboxes are full) the next valid message recep-
tion will lead to an overrun and a message will be
lost. The hardware signals the overrun condition
by setting the FOVR bit in the CRFR register.
Which message is lost depends on the configura-
tion of the FIFO:
– One 32-bit filter for the STDID[10:0], IDE, EX-
TID[17:0] and RTR bits.
– Two 16-bit filters for the STDID[10:0], RTR and
IDE bits.
– Four 8-bit filters for the STDID[10:3] bits. The
other bits are considered as don’t care.
– If the FIFO lock function is disabled (RFLM bit in
the CMCR register cleared) the last message
stored in the FIFO will be overwritten by the new
incoming message. In this case the latest mes-
sages will be always available to the application.
– One 16-bit filter and two 8-bit filters for filtering
the same set of bits as the 16 and 8-bit filters de-
scribed above.
– If the FIFO lock function is enabled (RFLM bit in
the CMCR register set) the most recent message
will be discarded and the software will have the
three oldest messages in the FIFO available.
Refer to Figure 149.
Furthermore, the filters can be configured in mask
mode or in identifier list mode.
Mask mode
Reception Related Interrupts
In mask mode the identifier registers are associat-
ed with mask registers specifying which bits of the
identifier are handled as “must match” or as “don’t
care”.
Once a message has been stored in the FIFO, the
FMP[1:0] bits are updated and an interrupt request
is generated if the FMPIE bit in the CIER register is
set.
Identifier List mode
When the FIFO becomes full (i.e. a third message
is stored) the FULL bit in the CRFR register is set
and an interrupt is generated if the FFIE bit in the
CIER register is set.
In identifier list mode, the mask registers are
used as identifier registers. Thus instead of defin-
ing an identifier and a mask, two identifiers are
specified, doubling the number of single identifi-
ers. All bits of the incoming identifier must match
the bits specified in the filter registers.
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STMICROELECTRONICS [ ST ]
