欢迎访问ic37.com |
会员登录 免费注册
发布采购

ST92F150JDV1Q6 参数 Datasheet PDF下载

ST92F150JDV1Q6图片预览
型号: ST92F150JDV1Q6
PDF下载: 下载PDF文件 查看货源
内容描述: 8月16日- BIT单电压闪存单片机系列内存, E3 TMEMULATED EEPROM , CAN 2.0B和J1850 BLPD [8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TMEMULATED EEPROM, CAN 2.0B AND J1850 BLPD]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 426 页 / 3830 K
品牌: STMICROELECTRONICS [ ST ]
 浏览型号ST92F150JDV1Q6的Datasheet PDF文件第320页浏览型号ST92F150JDV1Q6的Datasheet PDF文件第321页浏览型号ST92F150JDV1Q6的Datasheet PDF文件第322页浏览型号ST92F150JDV1Q6的Datasheet PDF文件第323页浏览型号ST92F150JDV1Q6的Datasheet PDF文件第325页浏览型号ST92F150JDV1Q6的Datasheet PDF文件第326页浏览型号ST92F150JDV1Q6的Datasheet PDF文件第327页浏览型号ST92F150JDV1Q6的Datasheet PDF文件第328页  
CONTROLLER AREA NETWORK (bxCAN)  
10.10 CONTROLLER AREA NETWORK (bxCAN)  
10.10.1 Introduction  
16-bit free running timer  
Configurable timer resolution  
Time Stamp sent in last two data bytes  
Management  
This peripheral Basic Extended CAN, named bx-  
CAN, interfaces the CAN network. It supports the  
CAN protocol version 2.0A and B. It has been de-  
signed to manage a high number of incoming mes-  
sages efficiently with a minimum CPU load. It also  
meets the priority requirements for transmit mes-  
sages.  
Maskable interrupts  
Software-efficient mailbox mapping at a unique  
address space  
For safety-critical applications, the CAN controller  
provides all hardware functions for supporting the  
CAN Time Triggered Communication option.  
10.10.3 General Description  
In today’s CAN applications, the number of nodes  
in a network is increasing and often several net-  
works are linked together via gateways. Typically  
the number of messages in the system (and thus  
to be handled by each node) has significantly in-  
creased. In addition to the application messages,  
Network Management and Diagnostic messages  
have been introduced.  
10.10.2 Main Features  
Supports CAN protocol version 2.0 A, B Active  
Bit rates up to 1Mbit/s  
Supports the Time Triggered Communication  
option  
Transmission  
– An enhanced filtering mechanism is required to  
handle each type of message.  
Three transmit mailboxes  
Configurable transmit priority  
Time Stamp on SOF transmission  
Reception  
Two receive FIFOs with three stages  
Eight scalable filter banks  
Identifier list feature  
Configurable FIFO overrun  
Time Stamp on SOF reception  
Time Triggered Communication Option  
Disable automatic retransmission mode  
Furthermore, application tasks require more CPU  
time, therefore real-time constraints caused by  
message reception have to be reduced.  
– A receive FIFO scheme allows the CPU to be  
dedicated to application tasks for a long time pe-  
riod without losing messages.  
The standard HLP (Higher Layer Protocol) based  
on standard CAN drivers requires an efficient in-  
terface to the CAN controller.  
– All mailboxes and registers are organized in 16-  
byte pages mapped at the same address and se-  
lected via a page select register.  
Figure 142. CAN Network Topology  
ST9 MCU  
Application  
CAN  
Controller  
CAN  
Rx  
CAN  
Tx  
CAN  
Transceiver  
CAN  
High  
CAN  
Low  
CAN Bus  
324/426  
9
 复制成功!