ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
CLOCK CONTROL REGISTERS (Cont’d)
Table 29. PLL Multiplication Factors
MX1
MX0
CLOCK2 x
PLL CONFIGURATION REGISTER (PLLCONF)
R246 - Read/Write
1
0
1
0
0
0
1
1
14
10
8
Register Page: 55
Reset Value: 0x00 x111
7
0
6
FREEN
0
MX1
MX0
0
DX2 DX1 DX0
Table 30. PLL Divider Factors
Bit 7 = FREEN: PLL Free Running Mode Enable
0: PLL Free Running Mode disabled
DX2
0
DX1
0
DX0
0
CK
PLL CLOCK/1
PLL CLOCK/2
PLL CLOCK/3
PLL CLOCK/4
PLL CLOCK/5
PLL CLOCK/6
PLL CLOCK/7
1: PLL Free Running Mode enabled
0
0
1
0
1
0
When this bit is set, even if the DX[2:0] bits are all
set to 1, the PLL is not stopped but provides a slow
frequency back-up clock, selectable by the
CSU_CKSEL bit of the CLK_FLAG register (with-
out needing to have the LOCK bit equal to ‘1’).
0
1
1
1
0
0
1
0
1
1
1
0
CLOCK2
(PLL OFF, Reset State)
1
1
1
Bits 5:4 = MX[1:0]: PLL Multiplication Factor.
Refer to Table 29 for multiplier settings.
WARNING: After these bits are modified, take
care that the PLL lock-in time has elapsed before
setting the CSU_CKSEL bit in the CLK_FLAG reg-
ister.
Bits 2:0 = DX[2:0]: PLL output clock divider factor.
Refer to Table 30 for divider settings.
135/426
9
STMICROELECTRONICS [ ST ]
