ST10F276E
Bootstrap loader
Error induced by the polling
The code used for the polling is the following:
WaitCom:
JNB P4.5,CAN_Boot
; if SOF detected on CAN, then go to
CAN
; loader
JB
BSET T6R
....
CAN_Boot:
BSET PWMCON0.0
P3.11,WaitCom
; Wait for start bit at RxD0
; Start Timer T6
; Start PWM Timer0
; (resolution is 1 CPU clk cycle)
JMPR cc_UC,WaitRecessiveBit
WaitDominantBit:
JB
P4.5,WaitDominantBit; wait for end of stuff bit
WaitRecessiveBit:
JNB P4.5,WaitRecessiveBit; wait for 1st dominant bit = Stuff
bit
CMPI1R1,#5
; Test if 5th stuff bit detected
JMPR cc_NE,WaitDominantBit; No, go back to count more
BCLR PWMCON.0
; Stop timer
; here the 5th stuff bit is detected:
; PT0 = 29 Bit_Time (25D and 4R)
Therefore the maximum error at the detection of the communication on CAN pin is:
(1 not taken + 1 taken jumps) + 1 taken jump + 1 bit set: (6) + 6 CPU clock cycles
The error at the detection for the 5th recessive bit is:
(1 taken jump) + 1 not taken jump + 1 compare + 1 bit clear: (4) + 6 CPU cycles
In the worst case, the induced error is 6 CPU clock cycles, so the polling could induce an
error of 6 timer ticks.
Error induced by the baud rate calculation
The content of the timer PT0 counter corresponds to 29 bit times, resulting in the following
equation:
PT0 = 58 x (BRP + 1) X (1 + Tseg1 + Tseg2)
where BRP, Tseg1 and Tseg2 are the field of the CAN Bit Timing register.
The CAN protocol specification recommends to implement a bit time composed of at least 8
time quanta (tq). This recommendation is applied here. Moreover, the maximum bit time
length is 25 tq. To ensure precision, the aim is to have the smallest Bit Rate Prescaler (BRP)
and the maximum number of tq in a bit time.
This gives the following ranges for PT0 according to BRP:
8 ≤ 1 + Tseg1 + Tseg2 ≤ 25
464 x (1 + BRP) ≤ PT0 ≤ 1450 x (1 + BRP)
Doc ID 12303 Rev 3
63/235
STMICROELECTRONICS [ ST ]
