ST10F276E
Bootstrap loader
Figure 9.
UART bootstrap loader sequence
234).
0ꢉ,ꢌꢇ
2X$ꢉ
ꢍꢀꢏ
ꢍꢁꢏ
ꢍꢇꢏ
ꢍꢈꢏ
4X$ꢉ
ꢍꢃꢏ
#30ꢐ)0
ꢈꢁ BYTES
USER SOFTWARE
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)NTꢌ "OOT 2/- ꢂ 4ESTꢅ&LASH "3,ꢅROUTINE
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1. BSL initialization time, > 1ms @ f
= 40 MHz
CPU
2. Zero byte (1 start bit, eight ‘0’ data bits, 1 stop bit), sent by host
3. Acknowledge byte, sent by ST10F276E
4. 32 bytes of code / data, sent by host
5. Caution: TxD0 is only driven a certain time after reception of the zero byte (1.3ms @ f
6. Internal Boot ROM / Test-Flash
= 40 MHz).
CPU
5.3.2
Entering bootstrap via UART
The ST10F276E enters BSL mode if pin P0L.4 is sampled low at the end of a hardware
reset. In this case, the built-in bootstrap loader is activated independently of the selected
bus mode. The bootstrap loader code is stored in a special Test-Flash; no part of the
standard mask ROM or Flash memory area is required for this.
After entering BSL mode and the respective initialization, the ST10F276E scans the RxD0
line to receive a zero byte, that is, 1 start bit, eight ‘0’ data bits and 1 stop bit. From the
duration of this zero byte, it calculates the corresponding baud rate factor with respect to the
current CPU clock, initializes the serial interface ASC0 accordingly and switches pin TxD0 to
output. Using this baud rate, an acknowledge byte is returned to the host that provides the
loaded data.
The acknowledge byte is D5h for the ST10F276E.
Doc ID 12303 Rev 3
55/235
STMICROELECTRONICS [ ST ]
