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ST10F276S-4T3 参数 Datasheet PDF下载

ST10F276S-4T3图片预览
型号: ST10F276S-4T3
PDF下载: 下载PDF文件 查看货源
内容描述: 16位MCU与MAC单元832 KB的闪存和68 KB的RAM [16-bit MCU with MAC unit 832 Kbyte Flash memory and 68 Kbyte RAM]
分类和应用: 闪存
文件页数/大小: 235 页 / 2491 K
品牌: STMICROELECTRONICS [ ST ]
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Bootstrap loader  
ST10F276E  
5.3.3  
ST10 Configuration in UART BSL (RS232 or K-Line)  
When the ST10F276E enters BSL mode on UART, the configuration shown in Table 30 is  
automatically set (values that deviate from the normal reset values are marked in bold).  
Table 30. ST10 configuration in UART BSL mode (RS232 or K-line)  
Function or register  
Watchdog timer  
Access  
Disabled  
Notes  
(1)  
Register SYSCON  
Context Pointer CP  
Register STKUN  
Stack Pointer SP  
Register STKOV  
Register BUSCON0  
Register S0CON  
Register S0BG  
P3.10 / TXD0  
0400H  
FA00H  
FA00H  
FA40H  
FC00H  
acc. to startup config.(2)  
8011H  
Initialized only if Bootstrap via UART  
Initialized only if Bootstrap via UART  
Initialized only if Bootstrap via UART  
Initialized only if Bootstrap via UART  
acc. to ‘00’ byte  
1’  
1’  
DP3.10  
1. In Bootstrap modes (standard or alternate) ROMEN, bit 10 of SYSCON, is always set regardless of EA pin  
level. BYTDIS, bit 9 of SYSCON, is set according to data bus width selection via Port0 configuration.  
2. BUSCON0 is initialized with 0000h, external bus disabled, if pin EA is high during reset. If pin EA is low  
during reset, BUSACT0, bit 10, and ALECTL0, bit 9, are set enabling the external bus with lengthened ALE  
signal. BTYP field, bit 7 and 6, is set according to Port0 configuration.  
Other than after a normal reset, the watchdog timer is disabled, so the bootstrap loading  
sequence is not time limited. Pin TxD0 is configured as output, so the ST10F276E can  
return the acknowledge byte. Even if the internal IFLASH is enabled, a code cannot be  
executed from it.  
5.3.4  
Loading the start-up code  
After sending the acknowledge byte, the BSL enters a loop to receive 32 bytes via ASC0.  
These bytes are stored sequentially into locations 00’FA40H through 00’FA5FH of the IRAM,  
allowing up to 16 instructions to be placed into the RAM area. To execute the loaded code  
the BSL then jumps to location 00’FA40H, that is, the first loaded instruction. The bootstrap  
loading sequence is now terminated; however, the ST10F276E remains in BSL mode. The  
initially loaded routine will most probably load additional code or data, as an average  
application is likely to require substantially more than 16 instructions. This second receive  
loop may directly use the pre-initialized interface ASC0 to receive data and store it in  
arbitrary user-defined locations.  
This second level of loaded code may be  
the final application code  
another, more sophisticated, loader routine that adds a transmission protocol to  
enhance the integrity of the loaded code or data  
a code sequence to change the system configuration and enable the bus interface to  
store the received data into external memory  
56/235  
Doc ID 12303 Rev 3  
 
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