ST10F276E
Electrical characteristics
Table 104. Multiplexed bus (continued)
fCPU = 40 MHz
TCL = 12.5ns
Variable CPU clock
1/2 TCL = 1 to 64 MHz
Symbol
Parameter
Min.
Max.
Min.
Max.
t22 CC Data valid to WR
t23 CC Data hold after WR
10 + tC
4 + tF
2TCL - 15 + tC
2TCL - 8.5 + tF
ns
ns
ALE rising edge after RD,
WR
-
-
t25 CC
15 + tF
10 + tF
- 4 - tA
-
2TCL - 10 + tF
2TCL - 15 + tF
- 4 - tA
ns
ns
ns
Address/Unlatched CS hold
t27 CC
after RD, WR
ALE falling edge to Latched
CS
t38 CC
10 - tA
10 - tA
Latched CS low to valid data
In
t39 SR
16.5 + tC+ 2tA
-
3TCL - 21 + tC + 2tA ns
ns
Latched CS hold after RD,
WR
t40 CC
27 + tF
7 + tA
- 5.5 + tA
3TCL - 10.5 + tF
TCL - 5.5 + tA
- 5.5 + tA
ALE fall. edge to RdCS,
t42 CC
-
-
ns
ns
ns
ns
ns
ns
ns
ns
WrCS (with RW delay)
ALE fall. edge to RdCS,
t43 CC
WrCS (no RW delay)
Address float after RdCS,
t44 CC
1.5
14
1.5
WrCS (with RW delay)(1)
Address float after RdCS,
t45 CC
TCL + 1.5
WrCS (no RW delay)
-
-
RdCS to valid data In
t46 SR
4 + tC
16.5 + tC
2TCL - 21 + tC
3TCL - 21 + tC
(with RW delay)
RdCS to valid data In
t47 SR
(no RW delay)
RdCS, WrCS low time
t48 CC
15.5 + tC
28 + tC
2TCL - 9.5 + tC
3TCL - 9.5 + tC
(with RW delay)
RdCS, WrCS low time
t49 CC
-
-
(no RW delay)
t50 CC Data valid to WrCS
t51 SR Data hold after RdCS
t52 SR Data float after RdCS(1)
10 + tC
2TCL - 15 + tC
ns
ns
ns
0
-
0
-
16.5 + tF
-
2TCL - 8.5 + tF
-
Address hold after
t54 CC
ns
ns
RdCS, WrCS
6 + tF
2TCL - 19 + tF
t56 CC Data hold after WrCS
1. Partially tested, guaranteed by design characterization.
Figures 57 to 60 present the different configurations of external memory cycle for a
multiplexed bus.
Doc ID 12303 Rev 3
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STMICROELECTRONICS [ ST ]
