System reset
ST10F276E
19.9
Reset summary
Table 61 summarizes the different reset events.
Table 61. Reset event
Event
RSTIN
WDTCON flags
Min
Max
1 ms (VREG)
1.2 ms
0
0
N
Asynch.
Asynch.
(Reson. + PLL)
10.2 ms
(Crystal + PLL)
-
-
1
1
1
1
1
1
1
1
0
0
Power-on Reset
0
1
x
0
0
0
0
1
x
x
0
1
0
1
N
x
1ms (VREG)
FORBIDDEN
Y
N
N
Y
Y
NOT APPLICABLE
Asynch.
Asynch.
Asynch.
Asynch.
500ns
500ns
500ns
500ns
-
-
-
-
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
Hardware Reset
(Asynchronous)
1032 + 12 TCL +
max(4 TCL, 500ns)
1
1
0
1
N
N
Synch.
Synch.
max (4 TCL, 500ns)
max (4 TCL, 500ns)
max (4 TCL, 500ns)
0
0
0
0
1
1
1
1
0
0
1032 + 12 TCL +
max(4 TCL, 500ns)
Short Hardware
Reset
1032 + 12 TCL +
max(4 TCL, 500ns)
1
1
0
1
Y
Y
Synch.
Synch.
0
0
0
0
1
1
1
1
0
0
(Synchronous) (1)
Activated by internal logic for 1024 TCL
1032 + 12 TCL +
max (4 TCL, 500ns)
max(4 TCL, 500ns)
Activated by internal logic for 1024 TCL
1032 + 12 TCL +
max(4 TCL, 500ns)
1
1
0
1
N
N
Synch.
Synch.
-
0
0
1
1
1
1
1
1
0
0
1032 + 12 TCL +
max(4 TCL, 500ns)
-
Long Hardware
Reset
(Synchronous)
1032 + 12 TCL +
max(4 TCL, 500ns)
-
1
1
0
1
Y
Y
Synch.
Synch.
0
0
1
1
1
1
1
1
0
0
Activated by internal logic only for 1024 TCL
1032 + 12 TCL +
max(4 TCL, 500ns)
-
Activated by internal logic only for 1024 TCL
128/235
Doc ID 12303 Rev 3
STMICROELECTRONICS [ ST ]
