System reset
ST10F276E
Figure 27. Asynchronous hardware RESET (EA = 0)
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t ꢃꢉNS
dꢃꢉꢉNS
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t ꢃꢉ NS
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4RANSPARENT
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ꢆ 4#,
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234
,ATCHING POINT OF PORTꢉ FOR
SYSTEM STARTꢅUP CONFIGURATION
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1. Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed); longer than 500ns to take
into account of Input Filter on RSTIN pin
2. 3 to 8 TCL depending on clock source selection.
Exit from asynchronous reset state
When the RSTIN pin is pulled high, the device restarts: as already mentioned, if internal
Flash is used, the restarting occurs after the embedded Flash initialization routine is
completed. The system configuration is latched from Port0: ALE, RD and WR/WRL pins are
driven to their inactive level. The ST10F276E starts program execution from memory
location 00'0000h in code segment 0. This starting location will typically point to the general
initialization routine. Timing of asynchronous Hardware Reset sequence are summarized in
Figure 26 and Figure 27.
19.3
Synchronous reset (warm reset)
A synchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at high
level. In order to properly activate the internal reset logic of the device, the RSTIN pin must
be held low, at least, during 4 TCL (2 periods of CPU clock): refer also to Section 19.1 for
details on minimum reset pulse duration. The I/O pins are set to high impedance and
RSTOUT pin is driven low. After RSTIN level is detected, a short duration of a maximum of
12 TCL (six periods of CPU clock) elapses, during which pending internal hold states are
cancelled and the current internal access cycle if any is completed. External bus cycle is
aborted. The internal pull-down of RSTIN pin is activated if bit BDRSTEN of SYSCON
register was previously set by software. Note that this bit is always cleared on power-on or
after a reset sequence.
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Doc ID 12303 Rev 3