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NAND256R4A0AZA6F 参数 Datasheet PDF下载

NAND256R4A0AZA6F图片预览
型号: NAND256R4A0AZA6F
PDF下载: 下载PDF文件 查看货源
内容描述: 128兆, 256兆, 512兆, 1千兆( X8 / X16 ), 528字节/字264页, 1.8V / 3V , NAND闪存 [128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories]
分类和应用: 闪存存储内存集成电路
文件页数/大小: 57 页 / 916 K
品牌: STMICROELECTRONICS [ ST ]
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A  
Table 21. AC Characteristics for Operations  
Alt.  
1.8V  
3V  
Symbol  
Parameter  
Unit  
Symbol  
Devices Devices  
t
Read Electronic Signature  
Read cycle  
Min  
Min  
Min  
10  
10  
20  
10  
10  
20  
ns  
ns  
ns  
ALLRL1  
Address Latch Low to  
Read Enable Low  
t
AR  
t
ALLRL2  
t
t
Ready/Busy High to Read Enable Low  
Read Busy time, 128Mb, 256Mb,  
BHRL  
RR  
Max  
12  
12  
µs  
512Mb Dual Die  
t
BLBH1  
Read Busy time, 512Mb, 1Gb  
Program Busy time  
Max  
Max  
Max  
Max  
Max  
Max  
Max  
Min  
15  
500  
3
12  
500  
3
µs  
µs  
ms  
µs  
µs  
µs  
µs  
ns  
ns  
Ready/Busy Low to  
Ready/Busy High  
t
t
t
t
PROG  
BLBH2  
BLBH3  
BLBH4  
t
Erase Busy time  
BERS  
Reset Busy time, during ready  
Reset Busy time, during read  
Reset Busy time, during program  
Reset Busy time, during erase  
5
5
5
5
Write Enable High to  
Ready/Busy High  
t
t
10  
500  
10  
0
10  
500  
10  
0
WHBH1  
RST  
t
t
Command Latch Low to Read Enable Low  
Data Hi-Z to Read Enable Low  
CLLRL  
CLR  
t
t
Min  
DZRL  
EHBH  
IR  
(1)  
(1)  
t
t
Chip Enable High to Ready/Busy High (E intercepted read)  
Max  
ns  
60 + t  
60 + t  
CRY  
r
r
(2)  
t
t
Min  
Max  
Max  
Max  
100  
20  
100  
20  
ns  
ns  
ns  
ns  
EHEL  
CEH  
Chip Enable High to Chip Enable Low  
t
t
Chip Enable High to Output Hi-Z  
Chip Enable Low to Output Valid  
Read Enable High to Ready/Busy Low  
EHQZ  
CHZ  
t
t
t
45  
45  
ELQV  
CEA  
t
RB  
100  
100  
RHBL  
Read Enable High to  
Read Enable High Hold time  
Read Enable Low  
t
t
Min  
15  
15  
ns  
ns  
RHRL  
REH  
Min  
15  
30  
15  
30  
t
t
Read Enable High to Output Hi-Z  
RHQZ  
RHZ  
Max  
Read Enable Low to  
Read Enable Pulse Width  
Read Enable High  
t
t
Min  
Min  
30  
60  
30  
50  
ns  
ns  
RLRH  
RP  
Read Enable Low to  
Read Cycle time  
Read Enable Low  
t
t
RLRL  
RC  
Read Enable Access time  
Read Enable Low to  
t
t
Max  
Max  
35  
12  
35  
12  
ns  
µs  
RLQV  
REA  
Output Valid  
(3)  
Read ES Access time  
Read Busy time, 128Mb, 256Mb,  
512Mb Dual Die  
Write Enable High to  
Ready/Busy High  
t
t
R
WHBH  
Read Busy time, 512Mb, 1Gb  
Max  
Max  
Min  
15  
100  
80  
12  
100  
60  
µs  
ns  
ns  
t
t
WB  
Write Enable High to Ready/Busy Low  
Write Enable High to Read Enable Low  
WHBL  
t
t
t
WHR  
WHRL  
Write Enable Low to  
Write Cycle time  
Write Enable Low  
t
Min  
60  
50  
ns  
WLWL  
WC  
Note: 1. The time to Ready depends on the value of the pull-up resistor tied to the Ready/Busy pin. See Figures 34, 35 and 36.  
2. To break the sequential read cycle, E must be held High for longer than tEHEL  
3. ES = Electronic Signature.  
.
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