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M95640-WMN6TP/P 参数 Datasheet PDF下载

M95640-WMN6TP/P图片预览
型号: M95640-WMN6TP/P
PDF下载: 下载PDF文件 查看货源
内容描述: [8KX8 SPI BUS SERIAL EEPROM, PDSO8, 0.169 INCH, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, TSSOP-8]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件页数/大小: 47 页 / 620 K
品牌: STMICROELECTRONICS [ ST ]
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M95640-W M95640-R M95640-DF  
Operating features  
The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C)  
is already low.  
Figure 6 also shows what happens if the rising and falling edges are not timed to coincide  
with Serial Clock (C) being low.  
5.4  
5.5  
Status Register  
The Status Register contains a number of status and control bits that can be read or set (as  
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a  
detailed description of the Status Register bits.  
Data protection and protocol control  
The device features the following data protection mechanisms:  
Before accepting the execution of the Write and Write Status Register instructions, the  
device checks whether the number of clock pulses comprised in the instructions is a  
multiple of eight.  
All instructions that modify data must be preceded by a Write Enable (WREN)  
instruction to set the Write Enable Latch (WEL) bit.  
The Block Protect (BP1, BP0) bits in the Status Register are used to configure part of  
the memory as read-only.  
The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the  
Status Register.  
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after  
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising  
edge of Serial Clock (C).  
Two points should be noted in the previous sentence:  
The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth  
bit of a data byte, depending on the instruction (except for Read Status Register  
(RDSR) and Read (READ) instructions).  
The “next rising edge of Serial Clock (C)” might (or might not) be the next bus  
transaction for some other device on the SPI bus.  
Table 2.  
Write-protected block size  
Status Register bits  
Protected block  
Protected array addresses  
BP1  
BP0  
0
0
1
1
0
1
0
1
none  
none  
Upper quarter  
Upper half  
1800h - 1FFFh  
1000h - 1FFFh  
0000h - 1FFFh  
Whole memory  
Doc ID 16877 Rev 16  
15/47  
 
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