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M95640-WMN6TP/P 参数 Datasheet PDF下载

M95640-WMN6TP/P图片预览
型号: M95640-WMN6TP/P
PDF下载: 下载PDF文件 查看货源
内容描述: [8KX8 SPI BUS SERIAL EEPROM, PDSO8, 0.169 INCH, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, TSSOP-8]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件页数/大小: 47 页 / 620 K
品牌: STMICROELECTRONICS [ ST ]
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M95640-W M95640-R M95640-DF  
Connecting to the SPI bus  
4
Connecting to the SPI bus  
All instructions, addresses and input data bytes are shifted in to the device, most significant  
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)  
after Chip Select (S) goes low.  
All output data bytes are shifted out of the device, most significant bit first. The Serial Data  
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction  
(such as the Read from Memory Array and Read Status Register instructions) have been  
clocked into the device.  
Figure 4.  
Bus master and memory devices on the SPI bus  
VSS  
VCC  
R
SDO  
SPI Interface with  
(CPOL, CPHA) =  
(0, 0) or (1, 1)  
SDI  
SCK  
VCC  
VCC  
VCC  
C
Q
D
C
Q
D
C Q D  
VSS  
VSS  
VSS  
SPI Bus Master  
SPI Memory  
Device  
SPI Memory  
Device  
SPI Memory  
Device  
R
R
R
CS3 CS2 CS1  
S
S
S
W
HOLD  
W
HOLD  
HOLD  
W
AI12836b  
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.  
Figure 4 shows an example of three memory devices connected to an SPI bus master. Only  
one memory device is selected at a time, so only one memory device drives the Serial Data  
Output (Q) line at a time. The other memory devices are high impedance.  
The pull-up resistor R (represented in Figure 4) ensures that a device is not selected if the  
Bus Master leaves the S line in the high impedance state.  
In applications where the Bus Master may leave all SPI bus lines in high impedance at the  
same time (for example, if the Bus Master is reset during the transmission of an instruction),  
the clock line (C) must be connected to an external pull-down resistor so that, if all  
inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled  
high): this ensures that S and C do not become high at the same time, and so, that the  
t
requirement is met. The typical value of R is 100 kΩ..  
SHCH  
Doc ID 16877 Rev 16  
11/47