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M95640-WMN6TP/P 参数 Datasheet PDF下载

M95640-WMN6TP/P图片预览
型号: M95640-WMN6TP/P
PDF下载: 下载PDF文件 查看货源
内容描述: [8KX8 SPI BUS SERIAL EEPROM, PDSO8, 0.169 INCH, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, TSSOP-8]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件页数/大小: 47 页 / 620 K
品牌: STMICROELECTRONICS [ ST ]
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Operating features  
M95640-W M95640-R M95640-DF  
5.1.4  
Power-down  
During power-down (continuous decrease of the V supply voltage below the minimum  
CC  
V
operating voltage defined under Operating conditions in Section 9: DC and AC  
CC  
parameters), the device must be:  
deselected (Chip Select S should be allowed to follow the voltage applied on V ),  
CC  
in Standby Power mode (there should not be any internal write cycle in progress).  
5.2  
Active Power and Standby Power modes  
When Chip Select (S) is low, the device is selected, and in the Active Power mode. The  
device consumes I  
.
CC  
When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in  
progress, the device then goes into the Standby Power mode, and the device consumption  
drops to I  
, as specified in DC characteristics (see Section 9: DC and AC parameters).  
CC1  
5.3  
Hold condition  
The Hold (HOLD) signal is used to pause any serial communications with the device without  
resetting the clocking sequence.  
To enter the Hold condition, the device must be selected, with Chip Select (S) low.  
During the Hold condition, the Serial Data Output (Q) is high impedance, and the Serial  
Data Input (D) and the Serial Clock (C) are Don’t Care.  
Normally, the device is kept selected for the whole duration of the Hold condition.  
Deselecting the device while it is in the Hold condition has the effect of resetting the state of  
the device, and this mechanism can be used if required to reset any processes that had  
(a)(b)  
been in progress.  
Figure 6.  
Hold condition activation  
c
HOLD  
Hold  
condition  
Hold  
condition  
ai02029E  
The Hold condition starts when the Hold (HOLD) signal is driven low when Serial Clock (C)  
is already low (as shown in Figure 6).  
a. This resets the internal logic, except the WEL and WIP bits of the Status Register.  
b. In the specific case where the device has shifted in a Write command (Inst + Address + data bytes, each data  
byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command.  
14/47  
Doc ID 16877 Rev 16  
 
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