Clock operation
Figure 13. Back-up mode alarm waveform
M41T81
V
CC
V
SO
trec
ABE and AFE Bits
AF Bit in Flags
Register
IRQ/FT/OUT/SQW
HIGH-Z
AI05663
Table 3.
RPT5
Alarm repeat modes
RPT4
RPT3
RPT2
RPT1
Alarm setting
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
Once per second
Once per minute
Once per hour
Once per day
Once per month
Once per year
3.5
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user
programs the watchdog timer by setting the desired amount of time-out into the Watchdog
Register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order
bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1
second, and 11 = 4 seconds. The amount of time-out is then determined to be the
multiplication of the five-bit multiplier value with the resolution. (For example: writing
00001110 in the Watchdog Register = 3*1, or 3 seconds). If the processor does not reset
the timer within the specified period, the M41T81 sets the WDF (Watchdog Flag) and
generates a watchdog interrupt.
The watchdog timer can be reset by having the microprocessor perform a WRITE of the
Watchdog Register. The time-out period then starts over.
Should the watchdog timer time-out, a value of 00h needs to be written to the Watchdog
Register in order to clear the IRQ/FT/OUT/SQW pin. This will also disable the watchdog
function until it is again programmed correctly. A READ of the Flags Register will reset the
Watchdog Flag (Bit D7; Register 0Fh).
The watchdog function is automatically disabled upon power-up and the Watchdog Register
is cleared. If the watchdog function is set, the frequency test function is activated, and the
SQWE Bit is '0,' the watchdog function prevails and the frequency test function is denied.
18/30
STMICROELECTRONICS [ ST ]
